/*****************************************************************************
*           Change Log
*  Date     | Change
*-----------+-----------------------------------------------------------------
* 30-Dec-85 | [1.279] Created
*****************************************************************************/
/* For now, the cycles must be as indicated: Iop = 0 thru 
   I8 = 8.  Additional cycles which never appear outside
   the instruction fetch cycle, i.e., those used for
   indexing, have higher numbers.

*/

/*
   The numbers below are hardwired into various instruction length checks
   throughout the simulator; Iop must be 0.
*/

#define Iop 0
#define I1  1
#define I2  2
#define I3  3
#define I4  4
#define I5  5
#define I6  6
#define I7  7
#define I8  8

/* The following numbers represent indexing cycles; they appear only within
   the instruction fetch mechanism and are not seen in the rest of the
   simulator
*/

#define I3X1   10
#define I3X10  11
#define I3X100 12
#define I6X1   13
#define I6X10  14
#define I6X100 15