* 001 * USAGE: 002 * 003 * ENTER AT 7 WITH THE A REGISTER (R 0) = 1130 EMULATED CORE BASE 004 * ADDRESS FOR LOAD MODE AND THE B REGISTER (R 1) = 1130 WRAPAROUND 005 * MASK. THE EMULATOR WILL RETURN TO THE CELL FOLLOWING THE LOAD 006 * MODE CALL FOR ALL 620/F MODE SERVICES. THE X REGISTER (R 2) 007 * WILL BE SET TO INDICATE THE NECESSARY ACTION. 008 * X = 0 -> AN 1130 WAIT INSTRUCTION WAS DECODED, OR AN 009 * UNDEFINED STATE OF THE MICROPROGRAM WAS ENTERED. 010 * X = 1 -> AN 1130 XIO INSTRUCTION WAS DECODED; THE B REGISTER 011 * CONTAINS THE EMULATED ADDRESS FROM THE XIO INSTRUCTION. 012 * X = 2 -> AN INTERRUPT WAS DETECTED IN 1130 MODE AND 620/F 013 * MODE WAS ENTERED TO PROCESS THE INTERRUPT. THE 620/F P 014 * REGISTER WAS SET TO POINT TO THE CELL AFTER THE LOAD MODE 015 * ENTRY, SO THAT 1130 EMULATOR 620 MODE SERVICE COULD SEND 016 * CONTROL BACK TO THE WCS. THE STEP KEY ALSO SETS X=2. 017 * 018 * ENTER AT X'A TO CONTINUE EMULATION AFTER A HALT, I/O INSTRUCTION 019 * OR INTERRUPT. THE A REGISTER (R 0) MUST BE RESET TO THE BASE OF 020 * 1130 EMULATED CORE. 021 * 022 * ENTER AT 3 TO CONTINUE EMULATION AFTER A SENSE INSTRUCTION 023 * WITH B (R 1) EQUAL TO THE DATA TO BE PUT INTO THE 1130 024 * ACCUMULATOR. THE A REGISTER (R 0) MUST BE RESET TO THE BASE 025 * ADDRESS OF EMULATED 1130 CORE. 026 * 027 * ENTER AT 4 WITH B (R 1) EQUAL TO THE 1130 INTERRUPT LEVEL TO 028 * REQUEST 1130 INTERRUPT. THE A REGISTER (R 0) MUST BE RESET 029 * TO THE BASE ADDRESS OF 1130 EMULATED CORE. 030 * 031 * ENTER AT 6 WITH A (R 0)=1130 BASE ADDRESS, B (R 1)=CHARACTER 032 * AND X (R 2)=BUFFER ADDRESS TO PERFORM 1132 PRINTER SCAN. 033 * X (R 2)=BUFFER ADDRESS+120 AFTER SCAN. 034 * 035 * ENTER AT X'B TO PUT 1130 A REGISTER INTO 620 A REGISTER. 036 * 037 * ENTER AT X'C TO PERFORM MEMORY - TO - MEMORY BLOCK MOVE. 038 * CALLING SEQUENCE: 039 * BCS PAGE1+C 040 * PZE/MZE FROM MZE - ALL FROM ONE WORD 041 * PZE/MZE TO MZE - ROTATED LEFT 4 BITS 042 * DATA LENGTH 043 * RETURN HERE WITH A (R 0) = ZERO. 044 * 045 * ENTER AT X'D TO SEARCH A TRANSLATE TABLE WITH A (R 0) = WORD TO 046 * SEARCH FOR, B (R 1) = TABLE ADDRESS. THE FIRST WORD OF THE TABLE 047 * IS EXPECTED TO BE THE TABLE LENGTH. AFTER THE SEARCH, B (R 1) 048 * IS SET TO THE RELATIVE LOCATION IN THE TABLE OF THE WORD (IF 049 * THE WORD IS FOUND), OR IS SET EQUAL TO THE TABLE LENGTH+1 IF 050 * THE WORD IS NOT FOUND. 051 * 052 * MORE ON NEXT PAGE 053 EJEC 054 * ENTER AT X'F WITH A (R 0) = 1130 EMULATED CORE BASE ADDRESS, 055 * B (R 1) = INTERRUPT LEVEL STATUS WORD TABLE ADDRESS FOR SENSE 056 * INTERRUPT. ILSW TABLE MUST CONTAIN ILSW'S FOR LEVELS 0 - 6. 057 * LEVEL 6 IS THE NORMAL OPERATION LEVEL, SO A SENSE INTERRUPT AT 058 * LEVEL 6 SHOULD RETURN A ZERO RESULT. 059 * THE ILSW FOR THE SENSED LEVEL IS RESET TO ZERO. 060 * 061 * REGISTERS USED BY THE 1130 EMULATOR: 062 * 063 BASE EQU 0 1130 MEMORY BASE ADDRESS (SUPPLIED ON ALL ENTRIES). 064 * NOTE BASE MUST BE THE SAME ON ALL ENTRIES (UNLESS THE 065 * EMULATED CORE AREA IS RELOCATED), AND MUST BE EVEN UNDER 066 * ALL CONDITIONS FOR THE DOUBLE-WORD REFERENCE INSTRUCTIONS 067 * TO WORK PROPERLY. THE SIGN BIT MUST NOT BE SET. 068 ADDR EQU 1 EMULATED 1130 ADDRESS: (1130 ADDRESS AND WRAP)+ BASE. 069 * NOTE ADDR IS NOT ALWAYS THE 1130 EMULATED ADDRESS, BUT 070 * IT IS ALWAYS SO WHEN IN 620/F MODE. 071 LVL EQU 1 INTERRUPT REQUEST LEVEL. 072 ILAILR EQU 6 ACTIVE AND REQUESTED INTERRUPT LEVELS: 073 * --------- ILA --------- --------- ILR --------- 074 * X 0 1 2 3 4 5 6 X 0 1 2 3 4 5 6 075 * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 076 * NOTE THAT LEVEL 6 IS THE NORMAL OPERATION LEVEL, AND IS 077 * ALWAYS SET ACTIVE SO THAT NO INTERRUPTS OCCUR AT LEVEL 6. 078 AIL EQU 7 CURRENTLY ACTIVE INTERRUPT LEVEL: 079 * --------- AIL ------ ---------- UNUSED -------- 080 * 0 1 2 3 4 5 6 081 * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 082 STAT EQU 8 STATUS REGISTER SAVE. 083 WRAP EQU 9 1130 WRAPAROUND MASK SUPPLIED BY THE 620 B REGISTER 084 * (R 1) ON THE LOAD MODE ENTRY. 085 ACC EQU X'A 1130 ACCUMULATOR. 086 EXT EQU X'B 1130 EXTENSION. 087 P620 EQU X'C P SAVE FOR 620/F MODE. 088 P1130 EQU X'D P SAVE FOR 1130 MODE DURING 620/F MODE SUPPORT. 089 W1 EQU X'E USED FREELY AS WORK REGISTERS. HARDWARE REQUIRES 090 W2 EQU X'F W1=X'E AND W2=X'F FOR MULTIPLY AND DIVIDE. 091 EJEC 092 DJUMP EQU X'20 DECODER JUMP BASE ADDRESS 093 PAGE1 EQU X'200 094 VINT1 EQU X'D1 FIRST STEP OF 620/F INTERRUPT SERVICE. 095 VSS2 EQU X'B4 620 MODE STANDARD STATE SS2. 096 VSS3M EQU X'2D 620 MODE STANDARD STATE SS3M. 097 VSTEP EQU X'1FF 620 MODE HALT LOOP. 098 * 099 * CONDITION TEST ROUTINE CALL MACRO 100 * 101 CTCALL MAC 102 GMSK /F(CTEST5),2(1),FS4,GF2,LB3,FF7, FS(0), 103 CMK0100,16(STAT) STAT.X'100,SAMPLE 104 EMAC 105 * 106 * GET TAG BITS TO OPERAND REGISTER, SAMPLE ALU. 107 * 108 GETTAG MAC 109 GMSK /N(P(1)),GF2,LB2,FFA,RF3,MKFCFF TAG -> OPR, SAMPLE ALU 110 EMAC 111 * 112 * GET TAG BITS TO OPERAND REGISTER, SAMPLE ALU, IF(P), INCP 113 * 114 GETTGL MAC 115 GMSK /N(P(1)),SF2,GF2,IM8,LB2,FFA,RF7,MKFCFF 116 EMAC 117 * 118 * ORIGIN AT NEXT MULTIPLE OF P(1). 119 * 120 MORG MAC 121 ORG *+P(1)-1 122 ORG */P(1)*P(1) 123 EMAC 124 * SPECIAL CASE OF MORG. 125 EVEN MAC 126 MORG 2 ORIGIN AT NEXT EVEN LOCATION. 127 EMAC 128 * 129 * ILLEGAL INSTRUCTIONS ALL BECOME WAITS. 130 * 131 WAITM MAC 132 GEN /N(E620M),FF3,MF1,WR1,AA2 ZERO -> 620 X. 133 EMAC 134 * 135 * UNUSED SPACE MACRO. 136 * 137 EMPTY MAC 138 WAITM 139 EMAC 140 EJEC 141 * 142 * CONTROL REACHES HERE VIA FIELD SELECT ADDRESSING FROM ADDRESS 143 * COMPUTATION. INACCESSIBLE ADDRESSES ARE USED FOR ENTRY POINTS. 144 * 145 MORG 32 146 OP00 EQU * 147 * SS2MX IS IDENTICAL TO SS2M BUT IS PLACED HERE BECAUSE IT APPEARS 148 * IN A TEST ADDRESS WITH BSC1. 149 SS2MX GEN /N(SS3M),SF1,IM8,RF4 INCP, IF(P) 150 XIO1 GMSK /N(XIO2),LB3,RF3,FFA,MKFFFE 1 -> OPERAND REGISTER 151 SHIFT1 GEN /N(SHIFT2),FFA,MF1,WR1,23(BASE), BASE->W1 152 C24(W1) 153 ************************************************************************ 154 * * 155 * ENTRY POINT TO CONTINUE THE 1130 PROGRAM WITH NEW ACCUMULATOR * 156 * * 157 RETRNA GEN /N(RETURN),FFA,MF1,WR1,BB1,24(ACC) R1->ACC * 158 ************************************************************************ 159 * * 160 * ENTRY POINT TO REQUEST 1130 INTERRUPT AT THE LEVEL SPECIFIED BY * 161 * THE 620 B REGISTER (R 1). * 162 * * 163 REQINT GEN /N(REQ1),RF1,FF9,23(BASE), BASE+P1130->P * 164 C24(P1130) * 165 ************************************************************************ 166 STS7 GMSK /N(STS8),SF1,GF4,IM3,LB3, RESET OVFL, OVR(BS), 167 CFFB,MKFFFC,16(W1) W1 & 3->ALU 168 ************************************************************************ 169 * * 170 * ENTRY POINT FOR 1132 PRINTER SCAN. * 171 * * 172 PSCAN1 GMSK /N(PSCAN2),SF1,IM5,LB3,RF3,FF9, BASE+32->OPR, OF(ALU) * 173 CMKFFDF,16(BASE) * 174 ************************************************************************ 175 * * 176 * 1130 LOAD MODE ENTRY POINT. * 177 * * 178 LMODE GEN /P(LMODE0+PAGE1),IM3,LA1,WR1, P->P620 * 179 C24(P620) * 180 ************************************************************************ 181 BSI1 GEN /N(BSI2),SF1,IM2,LA1,FF6,CF3, OVR(OS), P-BASE->ALU 182 C23(BASE) 183 BSC1 GEN /F(SS1M),2(8),FS7,RF1,24(ADDR) FS(6),ADDR->P 184 EJEC 185 ************************************************************************ 186 * * 187 * ENTRY POINT TO CONTINUE 1130 PROGRAM. * 188 * * 189 RETURN GEN /P(ENTR+PAGE1),SF2,GF4,IM4,RF1, BASE+P1130->P, * 190 CFF9,23(BASE),24(P1130) IF(ALU) * 191 ************************************************************************ 192 * * 193 * ENTRY POINT TO PUT 1130 A REGISTER INTO 620 A REGISTER. * 194 * * 195 GETREG GEN /P(VSS3M),SF2,GF4,IM8,RF4,FFA, ACC->R0, INCP, IF(P) * 196 CMF1,WR1,23(ACC),24(0) * 197 ************************************************************************ 198 * * 199 * ENTRY POINT FOR MEMORY - TO - MEMORY BLOCK MOVE. * 200 * * 201 MBM GEN /N(MBM1),SF1,IM9,RF4 AF(P),INCP * 202 ************************************************************************ 203 * * 204 * ENTRY POINT FOR TABLE SEARCH. * 205 * * 206 XLATE GEN /N(XLATE1),LA1,WR1,24(W2) P->W2 * 207 ************************************************************************ 208 MDX GEN /N(MDX1),FFA,MF1,WR1,23(BASE), BASE->ADDR 209 C24(ADDR) 210 ************************************************************************ 211 * * 212 * ENTRY POINT FOR SENSE INTERRUPT INSTRUCTION. * 213 * * 214 SENSEI GMSK /N(SENSI1),LB3,RF3,FFE,MKFEFF, ILAILR V X'100 -> OPR * 215 C16(ILAILR) * 216 ************************************************************************ 217 A1 GEN /N(A2),IM1 WAIT FOR OPERAND 218 AD1 GMSK /N(ADSD2),GF2,LB3,FF7,MK1, ADDR & 1, SAMPLE ALU 219 C16(ADDR) 220 S1 GMSK /N(S2),IM1,LB3,RF3,FFA,MKF7FF WAIT(M),X'800->OPR 221 SD1 GMSK /N(ADSD2),GF2,LB3,FF7,MK1, ADDR & 1, SAMPLE ALU 222 C16(ADDR) 223 M1 GEN /N(MUL2),RF3,VF1,24(ACC) ACC->OPR,SIGN->DSB 224 D1 GMSK /N(DIV1),IM1,LB3,RF3,FFA,MKFEFF X'100->OPR, WAIT(MEM) 225 EMPTY 226 EMPTY 227 LDA1 GEN /N(LDA2),SF1,IM8,RF4 IF(P),INCP 228 LDD1 GMSK /N(LDD2),GF2,LB3,FF7,MK1,16(ADDR) ADDR & 1, SAMPLE 229 STO1 GEN /N(STO2),SF1,IM2,24(ACC) OS(OVR),HOLD ACC FOR OS 230 STD1 GEN /N(STD2),SF1,IM2,24(ACC) OS(OVR),HOLD ACC FOR OS 231 AND1 GEN /N(AND2),SF1,IM8,RF4 IF(P), INCP 232 OR1 GEN /N(OR2),SF1,IM8,RF4 IF(P), INCP 233 EOR1 GEN /N(EOR2),SF1,IM8,RF4 IF(P), INCP 234 EMPTY 235 EJEC 236 ORG DJUMP DECODER REFERENCES NEXT 28 WORDS, 237 * EXCEPT THOSE MARKED 'EMPTY'. 238 OP00S WAITM OP = 0 239 OP00L WAITM OP = 0 240 XIOS GETTAG SHORT EXECUTE I/O SHORT 241 XIOL GETTGL LONG EXECUTE I/O LONG 242 SHIFT GETTAG SHIFT1 SHIFT INSTRUCTIONS. TAG -> OPR. 243 WAITS WAITM OP=6,7,A,B,16,17 244 SHORTS GETTAG SHORT A,AD,S,SD,M,D,LD,LDD, 245 LONGS GETTGL LONG STO,STD,AND,OR 246 EMPTY 247 LDS GEN /F(LDSRC),2(1),FS5 LOAD STATUS FSEL(1) 248 EMPTY 249 STS GEN /N(STS1),RF3,24(STAT) STORE STATUS STAT->OPR 250 BSIS GETTAG SHORT BRANCH & STORE IAR SHORT 251 BSIL CTCALL BSI LONG 252 BSCS CTCALL BSC SHORT 253 BSCL CTCALL BSC LONG 254 LDXS GETTAG LDXS1 LOAD INDEX SHORT. 255 LDXL GETTAG LDXL1 LOAD INDEX LONG. 256 STXS GETTAG STXS1 STORE INDEX SHORT. 257 STXL GETTGL STXL1 STORE INDEX LONG. 258 EMPTY 259 MDXSL GETTAG MDX MODIFY INDEX AND SKIP 260 EMPTY 261 WAITF WAITM OP = F (ILLEGAL) 262 EORS GETTAG SHORT EXCLUSIVE OR SHORT 263 EORL GETTGL LONG EXCLUSIVE OR LONG 264 WT1FS WAITM OP = 1F (ILLEGAL) SHORT 265 WT1FL WAITM OP = 1F (ILLEGAL) LONG 266 EJEC 267 * ADDRESS COMPUTATION SUBROUTINES 268 * 269 * 270 * COMPUTE EFFECTIVE ADDRESS AND FETCH OPERAND, LONG FORMAT 271 * 272 MORG 16 ADDREX, LNGNXI REF BY CND FSEL 273 ADDREX GEN /F(OP00),2(X'F),MT1,FSF,SF1, BASE+ADDR->ADDR, 274 CIM5,FF9,WR1,23(BASE),24(ADDR) OF(ALU) 275 LNGNXI GEN /N(LGNXI1),SF1,IM5,FF9,WR1, BASE+ADDR->ADDR, 276 C23(BASE),24(ADDR) OF(ALU) 277 LGNXI1 GEN /N(LGNXI2),IM1,FFA,MF1,WR1, WAIT(MEM), WRAP->ADDR 278 C23(WRAP),24(ADDR) 279 LGNXI2 GEN /N(ADDREX),LB1,FFB,MF1,WR1,BB1, MIR & WRAPAROUND->ADDR 280 C24(ADDR) 281 LONG GEN /N(LONG1),LB1,FFA,MF1,WR1,BB1, MIR(=Y) -> ADDR 282 C24(ADDR) 283 LONG1 GEN /S(ADDREX,LONGX),2(1),FSB,TF2, WRAP & ADDR->ADDR 284 CGF9,FFB,MF1,WR1,23(WRAP),24(ADDR) 285 EVEN 286 LONGX GEN /N(LONGX1),SF1,IM5,LB1,FF9,BB5, BASE+OLSE, OF(ALU) 287 C24(BASE) 288 LONGX1 GEN /N(LONGX2),GF2,IM1,RF3,SH1 WAIT(M),SAMPLE,0->OPR 289 LONGX2 GEN /N(LONG1),LB1,FF9,WR1,BB1, ADDR+MIR->ADDR 290 C24(ADDR) 291 * 292 * COMPUTE EFFECTIVE ADDRESS AND FETCH OPERAND, SHORT FORMAT 293 * 294 SHORT GMSK /N(SHORT1),LB2,RF3,FFA,MKFC00 TAG & DISP -> OPR 295 SHORT1 GEN /T(SHORTP,SHORTX),TF2,SF2,GF9, TEST ALUZ: 296 CIM5,LB1,FF9,BB5,24(BASE) T => SHORTP; 297 * F => OF(ALU = TAG+BASE), SHORTX 298 SHORTP GEN /N(SHRTP1),LA1,FF6,CF3,WR1, P-BASE -> ADDR 299 C23(BASE),24(ADDR) 300 EVEN 301 SHORTX GEN /N(SHRTX1),IM1,LB1,FFA,MF1,WR1, WAIT(MEM),ORSE->ADDR 302 CBB4,24(ADDR) 303 SHRTX1 GEN /N(SHRTR1),LB1,FF9,WR1,BB1, ADDR+MIR->ADDR 304 C24(ADDR) 305 SHRTP1 GEN /N(SHRTR1),LB1,FF9,WR1,BB4, ADDR+ORSE->ADDR 306 C24(ADDR) 307 SHRTR1 GEN /N(ADDREX),FFB,MF1,WR1,23(WRAP), WRAP & ADDR->ADDR 308 C24(ADDR) 309 EJEC 310 * CONDITION TEST ROUTINE. ON EXIT, QS=1 IF ANY SELECTED TEST 311 * PASSES, AND QS=0 IF ALL SELECTED TESTS FAIL. 312 * 313 MORG 16 314 CBS GEN /T(BSC1,SS2MX),TF2,GFF,LA1,CF3, P+1->ADDR,QS=>BSC1 315 CWR1,24(ADDR) NOT QS=>SS2MX 316 CBL GEN /T(CBL1,SS2M),TF3,SF3,GFF,IM8,RF4 INCP,QS=0=>CBL1; 317 * QS=>IF(P),SS2M 318 EVEN 319 CTEST5 GEN /F(CTEST4),2(1),FS9,GF2,24(ACC) FS(5),ACC->ALU,SAMPLE 320 CTST0A GMSK /N(CTST0B),SF1,GF4,LB3,RF3,FF7, RESET OVERFLOW, 321 CMKFEFF,16(STAT) STAT & FEFF -> OPR 322 EVEN 323 CTEST4 GEN /F(CTEST3),2(1),FS8,WF1,SH2 1->QS,FS(4) 324 CTST5A GEN /S(CBS,CTEST4),2(1),FSE,TF2,GF9, 1->QS, 325 CWF1,SH2 NOT ALUZ => CTEST4 326 EVEN 327 CTEST3 GEN /F(CTEST2),2(1),FS7 FS(3) 328 CTST4A GEN /S(CBS,CTEST3),2(1),FSE,TF2,GF7 NOT ALUS=>CTEST3 329 EVEN 330 CTEST2 GMSK /F(CTEST1),2(1),FS6,GF2,LB3,FF7, FS(2), 331 CMK1,16(ACC) ACC & 1, SAMPLE 332 CTST3A GEN /T(CTST3B,CTEST2),TF3,GF9 NOT ALUZ=>CTST3B 333 EVEN 334 CTEST1 GMSK /F(CTESTF),2(1),FS5,GF2,LB3,FF7, FS(1), 335 CMK0800,16(STAT) STAT & X'800,SAMPLE 336 CTST2A GEN /S(CBS,CTEST1),2(1),FSE,TF2,GF9 ACC ODD => CTEST1 337 EVEN 338 CTESTF GEN /F(CBS),2(1),FSE,WF1,SH1 FS(10), 0->QS 339 CTST1A GEN /S(CBS,CTESTF),2(1),FSE,TF2,GF9 CARRY => CTESTF 340 CTST0B GEN /T(CTST5A,CTEST5),TF2,GF9,LB1, OPR->STAT, 341 CFFA,MF1,WR1,24(STAT) OVFL => CTEST5 342 CTST3B GEN /S(CBS,CTEST2),2(1),FSE,TF3,GF7 ALUS => CTEST2 343 EJEC 344 * DIVIDE INSTRUCTION. 345 * 346 DIV1 GEN /N(DIV2),LB1,FFA,MF1,WR1,WF1,BB1, MIR->W2,MIRS->QS 347 C24(W2) 348 DIV2 GEN /T(DIV4,DIV3),TF3,GFF,VF1,24(ACC) ACC(15)->DSB,TEST QS 349 EVEN 350 DIV3 GEN /N(DIV4),FF6,CF3,WR1,SH1,23(W2), -W2 -> W2 351 C24(W2) 352 DIV4 GEN /T(DIV7,DIV5),TF3,GFA,FF6,CF3, -W2 -> W1, 353 CWR1,SH1,23(W2),24(W1) TEST DSB 354 EVEN 355 DIV5 GEN /N(DIV6),GF2,FF6,CF3,WR1,SH1, -EXT -> EXT 356 C23(EXT),24(EXT) 357 DIV7 GEN /N(DIV8),GF2,FF9,WR1,23(W1), ACC+W1->ACC, SAMPLE 358 C24(ACC) 359 DIV6 GEN /N(DIV7),FF6,CF1,WR1,SH1,23(ACC), -ACC+CARRY->ACC 360 C24(ACC) 361 DIV8 GMSK /T(DIV10,DIV9),TF2,GF7,LB3,RF2, -15 -> CNT, TEST ALUS 362 CFFA,MKF 363 EVEN 364 DIV9 GEN /N(DIV10),SF1,GF2,LB1,FFE,MF1, OPR V STAT -> STAT, 365 CWR1,24(STAT) SET OVERFLOW 366 DIV10 GEN /N(DIV11),RF3,24(EXT) EXT -> OPR 367 EVEN 368 DIV12 GEN /N(DIV13),GF2,24(ACC) ACC -> ALU, SAMPLE 369 DIV11 GEN /T(*,DIV12),TF3,GFC,MR1,LA2,RF5, DIVIDE STEP 370 CFF9,WR1,SC1,XF2,SH2,23(W2),24(ACC) 371 DIV13 GEN /T(DIV15,DIV14),TF3,GF7 TEST ALUS 372 EVEN 373 DIV14 GEN /N(DIV15),FF9,WR1,23(W2),24(ACC) ACC+W2 -> ACC 374 DIV15 GEN /T(DIV17,DIV16),TF2,GFA TEST NO DSB 375 EVEN 376 DIV16 GEN /T(DIV19,DIV18),TF3,GFF,FFA,MF1, ACC -> EXT 377 CWR1,23(ACC),24(EXT) 378 DIV17 GEN /T(DIV19,DIV18),TF2,GFF,FF6,CF3, -ACC -> EXT 379 CWR1,SH1,23(ACC),24(EXT) 380 EVEN 381 DIV18 GEN /N(SS3M),SF1,IM8,LB1,RF4,FF6,CF3, -OPR->ACC,IF(P),INCP 382 CWR1,SH1,24(ACC) 383 DIV19 GEN /N(SS3M),SF1,IM8,LB1,RF4,FFA,MF1, OPR->ACC,IF(P),INCP 384 CWR1,24(ACC) 385 EJEC 386 * INTERRUPT SERVICE, INSTRUCTION PIPELINE STANDARD CASES AND 387 * 620 MODE INTERFACE. 388 * 389 * THE STATES WHICH SELECT THE DECODER ALSO ENABLE INTERRUPTS. IF 390 * AN INTERRUPT IS DETECTED, AND AN INTERRUPT IS NOT BEING PROCESSED 391 * (CINTF=0), CONTROL GOES TO INTBAS+7. 392 * AT INTBAS+7, THE I/O CONTROL STORE MICROPROGRAM IS INITIATED, 393 * AND THE INTERRUPT IS CHECKED AGAIN. IF THE INTERRUPT SERVICE 394 * CAN PROCEED, CONTROL GOES TO INTBAS+1. IF THE INTERRUPT IS 395 * SUPRESSED BY DMA ACTIVITY, CONTROL GOES TO INTBAS AND THE 396 * INTERRUPT IS TRIED AGAIN AFTER THE NEXT INSTRUCTION. 397 * 398 MORG 16 399 INTBAS EQU * 400 SS1M GEN /N(SS2M),SF1,IM8 IF(P) 401 INT1 GEN /N(INT2),FFA,MF1,WR1,23(P620), P620->W1 402 C24(W1) 403 INT2 GEN /N(INT3),FF6,CF3,WR1,23(BASE), P1130-BASE->P1130 404 C24(P1130) 405 INT3 GMSK /N(E620I),RF3,LB3,FFA,MKFFFD 2->OPERAND 406 * STANDARD STATE INSTRUCTIONS. 407 * SS2M AND SS3M MUST HAVE THE SAME 5 HIGH ORDER BITS: THEY 408 * APPEAR TOGETHER IN A TEST ADDRESSING MICRO. 409 EVEN 410 SS2M GEN /N(SS3M),SF1,IM8,LB1,RF4,FFA,MF1 INCP,IF(P),OPR->ALU 411 SS2MS GEN /N(SS3M),SF1,IM8,LB1,RF4,FFA,MF1, STATUS->STAT,INCP,IF(P) 412 CWR1,BB3,24(STAT) 413 * SS3M DOES: SELECT AND RESET INTERRUPT FLAG, ENABLE INTERRUPTS, 414 * IBR -> I, DECODE. 415 EVEN 416 SS3M GEN /N(INTBAS),1(X'F),GF5,IM6 417 ORG INTBAS+7 418 IWAIT GEN 2(SS1M),1(7),MT1,GF4,MR1,IME, EN INT, DIS DEC, 419 CLA1,RF1,FFF,WR1,24(P1130) IO STRT, P-1->P,P1130 420 * BOSC IS PLACED HERE BECAUSE IT IS REFERENCED WITH SS1M USING 421 * FIELD SELECT ADDRESSING. 422 ORG SS1M+8 423 BOSC GEN /N(BOSC1),LA3,FFD,MF1,WR1, AIL V NOT ILAILR -> 424 C23(ILAILR),24(AIL) AIL 425 * CBL1 IS PLACED HERE BECAUSE IT APPEARS IN A TEST WITH SS2M 426 CBL1 GMSK /N(LONG),GF2,IM1,LB2,FFA,RF3, WAIT(MEM),SAMPLE, 427 CMKFCFF IR & X'0300->OPR 428 * STDEVN IS PLACED HERE BECAUSE IT APPEARS IN A TEST WITH SS2M 429 STDEVN GEN /N(SS3M),SF1,IM8,RF4,24(EXT) INCP,IF(P),EXT->ALU 430 * STATES E620(XX) ENTER 620 MODE. 431 E620I GEN /P(VINT1),IM3,LB1,FFA,MF1,WR1,AA2 OPR->R2 (X REG) 432 E620M GEN /N(E620M1),LA1,FF6,CF3,WR1, P-BASE->P1130 433 C23(BASE),24(P1130) 434 E620M1 GEN /P(VSS2),SF2,GF4,IM4,RF1,24(P620) P620->P, IF(ALU) 435 E620MV GEN /N(E620M),LB1,FFA,MF1,WR1,AA2 OPERAND -> 620 X. 436 * STATES LMODE ARE USED FOR LOAD MODE ENTRY. 437 LMODE0 GEN /N(LMODE1),FF3,MF1,WR1,24(ILAILR) 0->ILAILR 438 LMODE1 GEN /N(LMODE2),FF3,MF1,WR1,24(AIL) 0->AIL 439 LMODE2 GEN /N(LMODE3),SF1,IM4,RF1 R0->P, IF(ALU) (BASE) 440 LMODE3 GEN /N(LMODE4),FFA,MF1,WR1,BB1, R1 -> WRAP 441 C24(WRAP) 442 LMODE4 GEN /N(ENTR),WR1,SH1,24(STAT) 0 -> STAT 443 * STATES BOSC AND REQ MANAGE THE 1130 INTERRUPT STRUCTURE IN 444 * ILAILR AND AIL. SEE COMMENTS AT HEAD OF PROGRAM. 445 BOSC1 GMSK /N(BOSC2),LB3,RF3,FF7,MKFEFE, AIL & NOT X'101 -> OPR 446 C16(AIL) 447 BOSC2 GEN /N(BOSC3),LB1,FF5,MF1,WR1, NOT OPR -> ILAILR 448 C24(ILAILR) 449 BOSC3 GEN /N(BOSC4),LB1,FF5,MF1,WR1,BB7, NOT ORLZ -> W2 450 C24(W2) 451 BOSC4 GEN /N(BOSC5),FF3,WR1,24(LVL) -1 -> LVL 452 BOSC6 GEN /T(REQ1,BOSC5),TF2,GFF,CF3,WR1, LVL+1->LVL 453 C24(LVL) 454 EVEN 455 * BOSC5 AND BOSC6 LOOK FOR LEFTMOST SET BIT OF ILR. 456 BOSC5 GEN /N(BOSC6),LA2,WR1,WF1,24(W2) W2(L)->W2,ALU(15)->QS 457 REQ1 GEN /N(REQ2),RF2,FF6,SH1,23(LVL) -LVL-1->SC 458 REQ2 GEN /N(REQ3),LA2,RF3,WF1,24(ILAILR) ILAILR(L)->OPR,SIGN->QS 459 REQ3 GEN /N(REQ4),LB1,FFA,MF1,WR1,24(W2) OPR->W2 460 REQ4 GMSK /N(REQ5),LB3,RF3,FFA,MK7FFF X'8000->OPR 461 EVEN 462 REQ5 GEN /T(REQ6,REQ10),TF3,SF3,GFF,IM8, OPR->AIL,OPR(R) 463 CLB1,FFA,MF1,WR1,SC1,WF1,24(AIL) IF(P) IF QS 464 REQ7 GEN /N(REQ8),LB1,FFE,MF1,WR1, ILAILR V OPR -> ILAILR 465 C24(ILAILR) 466 REQ10 GEN /N(REQ11),SC1,WF0 OPR(L)->OPR 467 MORG 4 REQ6, REQ10, REQ11 468 REQ11 GEN /T(REQ12,REQ11),TF2,GFC,RF5,SC1,WF1 OPR(R)->OPR, INC SC 469 REQ6 GEN /T(REQ7,REQ5),TF2,GFC,LA2,RF5, W2(L)->W2,ALU(15)->QS 470 CWR1,WF1,24(W2) 471 REQ12 GEN /N(SS2M),LB1,FFE,MF1,WR1,BB5, ILAILR V OLSE -> ILAILR 472 C24(ILAILR) 473 REQ8 GEN /N(REQ9),LB1,FF7,MF1,WR1,BB5, ILAILR&NOT OLSE->ILAILR 474 C24(ILAILR) 475 REQ9 GEN /N(INTEN),LA1,RF3,FF6,CF3,24(BASE) P-BASE->OPR 476 * STATES INTEN INTERRUPT THE 1130 PROGRAM AT THE LEVEL SPECIFIED 477 * IN LVL. A BSI INDIRECT IS SIMULATED. THE UNBIASED 1130 P 478 * ADDRESS IS EXPECTED IN THE OPERAND REGISTER. 479 INTEN GEN /P(INTEN0+PAGE1),IM3,FF9,WR1, BASE+LVL->LVL 480 C23(BASE),24(LVL) 481 INTEN0 GMSK /N(INTEN1),SF1,IM5,LB3,FF9, LVL+8->ALU,OF(ALU) 482 CMKFFF7,16(LVL) 483 INTEN1 GEN /N(INTEN2),IM1,FFA,MF1,WR1, WAIT(MEM), WRAP->ADDR 484 C23(WRAP),24(ADDR) 485 INTEN2 GEN /N(INTEN3),LB1,FFB,MF1,WR1,BB1, MIR & ADDR->ADDR 486 C24(ADDR) 487 INTEN3 GEN /N(INTEN4),SF1,IM6,RF1,FF9, ADDR+BASE->P,OS(ALU) 488 C23(BASE),24(ADDR) 489 INTEN4 GEN /N(ENTR),SF1,IM8,LB1,RF4,FFA,MF1 IF(P), INCP, OPR->ALU 490 ENTR GMSK /N(ENTR1),GF2,LB3,FF7,MK100, STAT & X'100, SAMPLE 491 C16(STAT) 492 ENTR1 GEN /T(ENTRSO,ENTRRO),TF3,GF9 ALUZ => ENTRRO 493 ENTRSO GEN /N(SS3M),SF1,GF2,IM8,RF4 SET OVFL, IF(P), INCP 494 EVEN 495 ENTRRO GEN /N(SS3M),SF1,GF4,IM8,RF4 RESET OVFL, IF(P), INCP 496 EJEC 497 * LOAD INDEX INSTRUCTION. 498 * 499 MORG 16 LXLXNI, LDXLXI REF BY CND FSEL FROM LDXL1 500 LXLXNI GEN /N(LDXLXR),SF1,IM6,LB1,FF9,BB5, OLSE+BASE->ALU, 501 C24(BASE) OF(ALU) 502 LDXLXI GEN /N(LDXLX1),SF1,IM8,RF4,FFA,MF1,WR1, WRAP->ADDR, 503 C23(WRAP),24(ADDR) INCP, IF(P) 504 LDXLX1 GEN /N(LDXLX2),LB1,RF5,FFB,MF1,WR1,BB1, MIR & ADDR->ADDR, 505 C24(ADDR) INC SC 506 LDXLX2 GEN /N(LXLXNI),SF1,IM5,FF9,WR1,23(BASE), ADDR+BASE->ADDR, 507 C24(ADDR) OF(ALU) 508 LDXLXR GEN /T(SS3M,SS2M),TF2,SF1,GFC,IM8,LB1, TEST SHFT CNT, 509 CRF4,FFA,MF1,BB1 MIR->,INCP,IF(P) 510 LXLNX1 GEN /S(LDXPJ,LDXPJ),2(1),FSB,TF3,GFC,LB1, TEST SHFT CNT, 511 CRF3,FFB,MF1,WR1,BB1,24(ADDR) MIR.ADDR->ADDR,OPR 512 EVEN 513 LDXLNX GEN /N(LXLNX1),IM1,FFA,MF1,WR1,23(WRAP), WAIT(MEM), 514 C24(ADDR) WRAP->ADDR 515 LDXS1 GMSK /T(LDXSP,LDXSX),TF2,GF9,LB2,FFA,RF3, TAG & DISP -> OPR 516 CMKFC00 517 EVEN 518 LDXSX GEN /N(LDXSX1),SF1,IM6,LB1,FF9,BB5, OLSE+BASE->ALU, 519 C24(BASE) OF(ALU) 520 LDXSP GEN /N(LDXPJ),LB1,RF3,FFB,MF1,BB4, ORSE & WRAP->OPR 521 C24(WRAP) 522 LDXSX1 GEN /N(SS3M),SF1,IM8,LB1,RF4,FFA,MF1,BB4 ORSE->ALU(FOR OS), 523 * INCP,IF(P) 524 LDXL1 GMSK /S(LXLXNI,LDXLNX),2(1),FSB,TF3,GF9, CND FSEL(7) 525 CLB3,RF2,FFA,MK1 -2 -> CNT 526 MORG 16 LDXPJ, LXLNXI REF BY CND FSEL 527 LDXPJ GEN /N(SS2M),SF1,IM4,LB1,RF1,FF9,24(BASE) OPR+BASE->P,IF(ALU) 528 LXLNXI GEN /N(LDXLNX),SF1,IM5,RF5,FF9,23(BASE), INC CNT, OF(ALU), 529 C24(ADDR) BASE+ADDR->ALU 530 EJEC 531 * MEMORY - TO - MEMORY BLOCK MOVE. 532 * 533 MBM1 GEN /N(MBM2),SF1,IM9,LB1,RF4,FFA,MF1, AF(P),INCP,MIR->R0 534 CWR1,BB1,AA0 535 MBM2 GEN /N(MBMX),SF1,IM8,LB1,RF4,FFA,MF1, IF(P),INCP,MIR->W1, 536 CWR1,WF1,BB1,24(W1) ALU(15)->QS 537 MBMX GEN /N(MBM3),LB1,RF3,FFA,MF1,BB1 MIR->OPR 538 MBM3 GEN /N(MBM4),FFF,WR1,24(W1) W1-1->W1 539 MBM4 GEN /N(MBM5),LA1,WR1,24(W2) P->W2 540 MBM5 GEN /N(MBM6),IM1,RF1,FFF,VF1,AA0 R0-1->P,R0(15)->DSB 541 MBM6 GEN /N(MBM7),LB1,FFA,MF1,WR1,BB0,AA0 OPR->R0 542 EVEN 543 MBM11 GEN /N(MBM19),IM1,LB1,FFA,MF1 WAIT(M),OPR->ALU 544 MBM7 GEN /T(MBM8,MBM12),TF3,SF1,GFF,IM9, OF(P),INCP,OPR->ALU 545 CLB1,RF4,FFA,MF1,BB0 546 EVEN 547 MBM12 GEN /N(MBM13),GF2,IM1,FFF,WR1,AA0 WAIT(M),R0-1->R0,SAMPLE 548 MBM8 GEN /N(MBM9),GF2,FFF,WR1,AA0 R0-1->R0,SAMPLE ALU 549 MBM9 GEN /T(MBM10,MBM18),TF3,SF2,GF7,IM6, CND(NO ALUS) OS(ALU), 550 CCF3,WR1,24(W1) W1+1->W1 551 MBM13 GEN /N(MBM14),LB1,RF3,FFA,MF1,BB1 MIR->OPR 552 MBM14 GMSK /N(MBM15),LB3,RF2,FFA,MK3 -4->SC 553 EVEN 554 MBM15 GEN /T(MBM16,*),TF2,GFC,RF5,SC1 OPR(L),INC SC, TEST SC 555 MBM16 GEN /T(MBM17,MBM18),TF3,SF2,GF7,IM6, CND(NO ALUS) OS(ALU), 556 CCF3,WR1,24(W1) W1+1->W1 557 MORG 4 558 MBM18 GEN /P(VSS3M),SF2,GF4,IM4,RF1,CF3, IF(ALU),W2+1->P 559 C24(W2) 560 MBM17 GEN /T(MBM7,MBM11),TF3,GFA,LB1, OPR->ALU,TEST DSB 561 CFFA,MF1 562 MBM10 GEN /T(MBM7,MBM11),TF3,GFA,LB1,RF3, MIR->OPR,TEST DSB 563 CFFA,MF1,BB1 564 MBM19 GEN /N(MBM16),GF2,FFF,WR1,AA0 R0-1->R0,SAMPLE 565 EJEC 566 * MODIFY INDEX AND SKIP INSTRUCTION. 567 * 568 MORG 16 MDXXS1, MDXXL1 REFERENCED BY CONDITIONAL FSEL 569 MDXXS1 GMSK /N(MDXXS2),LB2,RF3,FFA,MKFC00 IR & 3FF->OPR 570 MDXXL1 GEN /F(MDXXL3),2(1),FSB,LB1,RF7,FFA,MF1, MIR->W1 & OPR, 571 CWR1,BB1,24(W1) FSEL(7), INCP 572 MDXC1 GEN /T(MDXC2,MDXC3),TF2,SF1,GF9,IM5, OF(ALU), BASE+W1 573 CFF9,23(BASE),24(W1) 574 MDXXS2 GEN /N(MDXC3),GF2,IM1,FF3,MF1 WAIT(MEM),0->ALU, 575 * SAMPLE 576 MORG 4 MDXSKP MUST BE EVEN, MORG 16 WITH MDXNI,MDXC8 577 MDXSKP GEN /N(SS2M),SF1,IM8,RF4,LB1,FFA,MF1 IF(P),INCP,OPR-> 578 MDXC8 GEN /N(MDXC9),GF2,LB1,FF6,MF1,24(W1) W1 XOR OPR, SAMPLE 579 MDXNI GEN /N(SS2M),SF1,IM8,LB1,FFA,MF1 IF(P), OPR->ALU 580 MDX1 GEN /S(MDXXS1,MDXNX),2(1),FSE,TF3,SF2,GF9, CND OF(A),FSEL(10) 581 CIM5,LB1,FF9,WR1,BB5,24(ADDR) OLSE+ADDR->ADDR 582 EVEN 583 MDXNX GMSK /F(MDXP),2(1),FSE,LB2,RF3,FFA,MKFC00 IR&3FF->OPR,FS(10) 584 MDXNX2 GEN /N(MDXC1),LB1,FFB,MF1,WR1,BB1,24(W1) MIR & W1->W1 585 EVEN 586 MDXP GEN /N(SS2M),SF1,IM4,LB1,LA1,RF1,FF9,BB4 P+ORSE->P,IF(ALU) 587 MDXNX1 GEN /N(MDXNX2),IM1,RF4,FFA,MF1,WR1, WAIT(M),WRAP->W1, 588 C23(WRAP),24(W1) INCP 589 EVEN 590 MDXXL3 GEN /N(MDXC3),IM1 WAIT(MEM) 591 MDXXL2 GEN /N(MDXC1),FFB,MF1,WR1,23(WRAP),24(W1) WRAP & W1->W1 592 EVEN 593 MDXC3 GEN /S(MDXC5,MDXC6),2(1),FSB,TF3,GF9,LB1, MIR->W1, 594 CFFA,MF1,WR1,BB1,24(W1) FSEL(7) IF NO ALUZ 595 MDXC2 GEN /N(MDXC3),IM1,FF9,WR1,23(W1),24(ADDR) WAIT(M), 596 * W1+ADDR->ADDR 597 MORG 16 MDXC5, MDXC4 REF BY CND FSEL 598 MDXC5 GEN /N(MDXC7),GF2,LB1,RF3,FF9,24(W1) OPR+W1->OPR,SAMPLE 599 MDXC4 GEN /N(MDXC5),IM1,AB3,BB1,24(W1) "MIR"->BB,WAIT(M) 600 MDXC6 GEN /N(MDXC7),GF2,LB1,RF3,FF9,BB4,24(W1) ORSE+W1->OPR,SAMPL 601 MDXC7 GEN /T(MDXC8,MDXSKP),TF3,SF3,GF9,IM6, CND OS(ALU), 602 C24(ADDR) ADDR->ALU 603 MDXC9 GEN /T(MDXNI,MDXSKP),TF3,GF7,SF1,IM6, OS(ALU), 604 C24(ADDR) ADDR->ALU 605 EJEC 606 * MULTIPLY INSTRUCTION. 607 * 608 MUL2 GEN /N(MUL3),FF3,MF1,WR1,SC1,24(W1) 0->W1,LFT CIRC OPR 609 MUL3 GMSK /N(MUL4),IM1,LB3,RF2,FFA,MK000E -14->CNTR, WAIT(M) 610 MUL4 GEN /N(MUL5),LB1,FFA,MF1,WR1,BB1,24(W2) MIR->W2 611 MUL5 GEN /N(MUL6),MR1,FF3,MF1,WR1,SC1,WF1, 0->ACC,CRC RT OPR, 612 C24(ACC) OPR(1)->BAD(0) 613 MUL6 GEN /N(MUL7),MR1,RF5,FF9,WR1,SC1,WF1,XF1, ACC+(W1, W2)->ACC, 614 C24(ACC) RT OPR, OPR(1)->BAD(0), INC CNTR 615 EVEN 616 MUL7 GEN /T(MUL8,*),TF2,GFC,MR1,LA3,RF5,FF9, ACC+(W1, W2)->ACC, 617 CWR1,SC1,WF1,XF1,24(ACC) MULS-> DLA(15), RT ACC, RT OPR, 618 * DFA(0)->OPR(15), OPR(1)->BAD(0), 619 * INC CNTR, TEST CNTR = -1 620 MUL8 GEN /T(MUL10,MUL9),TF3,GFA,LA3,WR1,SC1, RT A, MUL SGN->A15 621 CWF1,XF1,24(ACC) RT OPR,DFA(0)->OPR(15),DSB=>MUL9 622 EVEN 623 MUL9 GEN /N(MUL10),FF6,CF3,WR1,23(W2),24(ACC) ACC-W2->ACC 624 MUL10 GEN /N(SHFTRX),SF1,IM8,LA3,RF4,WR1,SC1, RT ACC, A15->A15, 625 CWF1,XF1,SH2,24(ACC) RT OPR,DFA(0)->OPR(15),INCP,IF(P) 626 EJEC 627 * 1132 PRINTER SCAN ROUTINE. 628 * 629 PSCAN2 GEN /N(PSCAN3),LB1,FFA,MF1,WR1,24(W1) OPR->W1 630 PSCAN3 GMSK /N(PSCAN4),LB3,RF3,FFA,MK0077 -120->OPR 631 PSCAN4 GMSK /N(PSCAN5),IM1,LB3,RF2,FFA,MK000F -16->SC, WAIT(M) 632 PSCAN5 GEN /N(PSCAN6),LB1,FFA,MF1,WR1,WF1, MIR->W2, ALU(15)->QS 633 CBB1,24(W2) 634 PSCAN7 GEN /T(PSCAN9,PSCAN8),TF3,SF3,GFF, OS(ALU) IF QS, R2->ALU 635 CIM6,AA2 NOTE: R2 IS BUFFER ADDR 636 EVEN 637 PSCAN6 GEN /N(PSCAN7),GF2,LB1,RF3,FF9,CF3, OPR+1->OPR, SAMPLE 638 CSH1 639 PSCANX GEN /P(VSS3M),SF2,GF4,IM8,RF4 INCP, IF(P) 640 EVEN 641 PSCAN8 GEN /N(PSCAN9),IM1,AA1 WAIT(M),R1->ALU 642 PSCAN9 GEN /T(PSCANB,PSCANA),TF3,GFC,RF5, R2+1->R2, INC SC 643 CCF3,WR1,AA2 644 EVEN 645 PSCANA GEN /N(PSCAN4),SF1,IM5,CF3,WR1,24(W1) W1+1->W1, OF(ALU) 646 PSCANB GEN /T(PSCANX,PSCAN6),TF2,GF9,LA2, W2(L)->W2, ALU(15)->QS 647 CWR1,WF1,24(W2) 648 EJEC 649 * SHIFT INSTRUCTIONS. 650 * 651 * THIS IS THE SHIFT COUNT COMPUTATION. 652 SHIFT2 GEN /T(SHFTDF,SHFTX),TF2,SF2,GF9,IM5, 0->QS,ALUZ=>SHFTDF; 653 CLB1,FF9,WR1,WF1,BB5,24(W1) NO ALUZ->OF(TAG+W1),=>SHFTX 654 SHFTDF GMSK /N(SHIFT3),LB2,RF3,FFA,MKFFC0 LOW 6 (DISP) -> OPR 655 EVEN 656 SHFTX GEN /N(SHFTX1),IM1,WF1,SH2 WAIT(INDEX), 1->QS 657 SHFTX1 GEN /N(SHFTX2),LB1,FFA,MF1,WR1,BB1, MIR->ADDR 658 C24(ADDR) 659 SHFTX2 GMSK /N(SHIFT3),LB3,RF3,FF7,MK3F, LOW 6 (ADDR) -> OPR 660 C16(ADDR) 661 * SHIFT3 DOES: -OPR -> ADDR AND SHFT, SAMPLE ALU CONDITIONALS. 662 SHIFT3 GEN /F(SHFTL),2(1),FSF,GF2,LB1,RF2,FF6,CF3,WR1,SH1,24(ADDR) 663 MORG 16 SHFTL0-SHFTL3 REF BY CND FSEL FROM SHFTL 664 SHFTL0 GEN /T(*,SHFTLX),TF3,GFC,LA2,RF5,WR1,VF1, SHIFT ACC LEFT 665 C24(ACC) 666 SHFTL1 GEN /T(SHFT11,SHFTL0),TF2,GFF,FFC,CF3,WR1, TEST QS, 667 C24(W1) W1+W1+1 -> W1 668 SHFTL2 GEN /T(*,SHFTLX),TF3,GFC,LA2,RF5,WR1,SC1, SHIFT ACC&OPR LEFT 669 CVF1,XF3,SH2,24(ACC) 670 SHFTL3 GEN /T(SHFT31,SHFTL2),TF2,GFF,FFC,CF3,WR1, TEST QS, 671 C24(W1) W1+W1+1 -> W1 672 EVEN 673 SHFTLX GEN /N(SHFMSK),LB1,FFA,MF1,WR1,24(EXT) OPR -> EXT 674 SHFT11 GEN /N(SHFT12),WF1,24(ACC) ACC(15)->QS 675 SHFT12 GEN /T(SHFT13,SHFDR1),TF3,GFF,CF3, ADDR+1->ADDR, 676 CWR1,24(ADDR) TEST QS 677 SHFT13 GEN /T(SHFT12,SHFMR1),TF3,GFC,LA2,RF5,WR1, ACC(L)->ACC,INCSC, 678 CWF1,24(ACC) ALUS->QS,TEST SC 679 SHFT31 GEN /N(SHFT32),WF1,24(ACC) ACC(S)->QS 680 SHFT32 GEN /T(SHFT33,SHFDR1),TF3,GFF,CF3, ADDR+1->ADDR, 681 CWR1,24(ADDR) TEST QS 682 EVEN 683 SHFDR1 GEN /N(SHFMR1),FFF,WR1,24(ADDR) ADDR-1->ADDR 684 SHFT33 GEN /T(SHFT31,SHFMR1),TF3,GFC,LA2,RF5,WR1, SHFT ACC&OPR LEFT, 685 CSC1,XF3,SH2,24(ACC) TEST SC,INC SC 686 EVEN 687 SHFMR1 GEN /N(SHFTBS),VF1,24(ADDR) ADDR(15)->DSB 688 SHFTBS GEN /N(SHFTM),SF2,IM7,LA3,24(W1) RE/2, 1->BYTA, 689 * BS(ALU) 690 * SS3MX IS IDENTICAL TO SS3M BUT IS PLACED HERE DUE TO 691 * ADDRESSING RESTRICTIONS. 692 EVEN 693 SS3MX GEN /N(INTBAS),1(X'F),GF5,IM6 694 SHFTM GEN /N(SHFTLX),IM1,FF6,CF3,SH1,24(ADDR) WAIT(M),-ADDR->ALU 695 MORG 16 SHFTR0-SHFTR3 REF BY CND FSEL FROM SHFTR 696 SHFTR0 GEN /T(*,SHFTRX),TF3,SF3,GFC,IM8,LA3,RF5,WR1,SH4,24(ACC) 697 SHFTR1 GEN /T(*,SHFTRX),TF3,SF3,GFC,IM8,LA3,RF5,WR1,SH4,24(ACC) 698 SHFTR2 GEN /T(*,SHFTRX),TF3,SF3,GFC,IM8,LA3,RF5, 699 CWR1,SC1,WF1,XF1,SH2,24(ACC) 700 SHFTR3 GEN /T(*,SHFTRX),TF3,SF3,GFC,IM8,LA3,RF5, 701 CWR1,SC1,WF1,XF1,SH3,24(ACC) 702 * SHFTRX IS SIMILAR TO SS3M, AND IS PUT HERE DUE TO 703 * ADDRESSING RESTRICTIONS WHEN USING CONDITIONAL FIELD SELECTION. 704 * IN ADDITION TO EVERYTHING THAT SS3M DOES, SHFTRX DOES: OPR->EXT. 705 * SHFTRX IS ALSO USED BY THE MULTIPLY ROUTINE. 706 EVEN 707 SHFTRX GEN /N(INTBAS),1(X'F),GF5,IM6,LB1,FFA,MF1,WR1,24(EXT) 708 SHFMSK GMSK /T(SHFCOM,SHFARG),TF3,GFA,LB3,RF3, CARRY MASK (X'800) 709 CFFA,MKF7FF -> OPR 710 * SHIFT INSTRUCTIONS COME HERE WITH THE NEGATIVE OF THE SHIFT 711 * COUNT IN THE SHIFT COUNT REGISTER AND ADDR. NO SHIFTING IS DONE 712 * IF THE SHIFT COUNT IS ZERO. 713 * SHFTL AND SHFTR MUST BE KEPT TOGETHER: THEY ARE FIELD SELECT 714 * ADDRESSED. SHFTL AND SHFTR DO THE SAME THING TO LEFT AND 715 * RIGHT SHIFT INSTRUCTIONS RESPECTIVELY: RB->OPR, INCP, 716 * FIELD SELECT (7-6) IF NOT ALUZ, IF(P) IF ALUZ. 717 EVEN 718 SHFTL GEN /S(SHFTL0,SS3MX),2(3),FSA,TF3,SF3,GF9,IM8,RF7,24(EXT) 719 SHFTR GEN /S(SHFTR0,SHFTRX),2(3),FSA,TF3,SF3,GF9,IM8,RF7,24(EXT) 720 EVEN 721 SHFARG GEN /N(SS3M),SF1,IM8,LB1,FF1,WR1,24(STAT) IF(P), CARRY = 1 722 SHFCOM GEN /N(SS3M),SF1,IM8,LB1,FF7,MF1,WR1, IF(P), CARRY = 0 723 C24(STAT) 724 EJEC 725 * STORE STATUS INSTRUCTION. 726 * 727 STS1 GEN /N(STS2),LB1,RF3,FFA,MF1,BB5 OLSE->OPR (OVFL->LSB) 728 STS2 GEN /N(STS3),WR1,SC1,WF1,SH2,24(W1) OVFL->O(15),1'S->W1 729 STS3 GEN /N(STS4),LA3,SC1,WF1,XF2,24(W1) OVFL->O(15), 730 * CARRY->O(1),1->BYTA 731 STS4 GEN /N(STS5),SC1,WF1,XF2 OVFL->O(15),CARRY->O(0) 732 STS5 GEN /N(STS6),SC1,WR1,SH1,24(STAT) OVFL->O(0),CARRY->O(1), 733 * 0->STAT 734 STS6 GEN /F(STSS1),2(1),FSE,LB1,FFA,MF1, OPR->W1,FSEL(10) 735 CWR1,24(W1) 736 EVEN 737 STSS1 GETTAG SHORT 738 STSL1 GETTGL LONG 739 STS8 GMSK /N(SS3M),SF1,IM8,RF4,LB3,FF7, IF(P),INCP,W1&3->ALU 740 CMK3,16(W1) 741 EJEC 742 * STORE INDEX INSTRUCTION. 743 * 744 STXL1 GEN /N(STXL2),LB1,FFA,MF1,WR1,BB1,24(ADDR) MIR -> ADDR 745 STXL2 GEN /N(STXL3),FFB,MF1,WR1,23(WRAP),24(ADDR) WRAP & ADDR->ADDR 746 * STXL3 DOES: TEST ALUZ: T=> STXLP; F=> OF(OLSE+BASE),FSEL(7)->STXLX 747 STXL3 GEN /S(STXLX,STXLP),2(1),FSB,TF3,SF2,GF9,IM5,LB1,FF9,BB5, 748 C24(BASE) 749 MORG 4 STXLR, STXLI, STXLPI REF BY FSEL 750 STXLR GEN /N(STXLR1),SF1,IM6,FF9,23(BASE), OS(ALU), 751 C24(ADDR) BASE+ADDR->ALU 752 STXLI GEN /N(STXLI1),IM1,FFA,MF1,WR1,23(WRAP), WAIT(MEM), 753 C24(ADDR) WRAP->ADDR 754 STXLPI GEN /N(STXLI),SF1,IM5,FF9,WR1,23(BASE), OF(ALU), 755 C24(ADDR) BASE+ADDR->ADDR 756 STXLI1 GEN /N(STXLR),LB1,FFB,MF1,WR1,BB1,24(ADDR) MIR & ADDR->ADDR 757 MORG 16 STXLX, STXLX1 REF BY CND FSEL 758 STXLX GEN /N(STXLX2),IM1 WAIT(MEM=INDEX) 759 STXLX1 GEN /N(STXLX2),SF1,IM5,FF9,WR1,23(BASE), OF(ALU), 760 C24(ADDR) BASE+ADDR->ADDR 761 STXLX2 GEN /F(STXLR),2(1),FSB,LB1,RF3,FFA,MF1,BB1 MIR->OPR, FSEL(7) 762 * NOTE: DON'T INITIATE MEMORY AT STXLR1. LET MPLE SETTLE. 763 STXLR1 GEN /N(SS2M),LB1,FFA,MF1 OPR->ALU 764 * STXLP MUST HAVE THE SAME HIGH-ORDER 5 BITS AS STXLX 765 EVEN 766 STXLP GEN /F(STXLR),2(2),FSA,LA1,RF3,FF6,CF3, P-BASE->OPR, 767 C23(BASE) FSEL(7) 768 STXS1 GMSK /N(STXS2),LB2,FFA,RF3,MKFC00 TAG & DISP -> OPR 769 * STXS2 DOES: BASE+OLSE -> ALU, OF(ALU) IF NOT ALUZ 770 STXS2 GEN /T(STXS3,STXS3),TF2,SF2,GF9,IM5,LB1,FF9,BB5,24(BASE) 771 EVEN 772 STXS3 GEN /N(STXS4),LA1,FF6,CF3,WR1,23(BASE), P-BASE->ADDR 773 C24(ADDR) 774 STXS4 GEN /N(STXS5),LB1,RF3,FF9,BB4,24(ADDR) ADDR+ORSE->OPR 775 STXS5 GEN /N(STXS6),LB1,RF3,FFB,MF1,24(WRAP) OPR & WRAP->OPR 776 STXS6 GEN /T(STXSP,STXSX),TF2,SF1,GF9,IM6,LB1, OPR+BASE->OPR, 777 CRF3,FF9,24(BASE) OS(ALU) 778 EVEN 779 * NOTE: DON'T INITIATE MEMORY AT STXSX OR STXSP. LET MPLE SETTLE. 780 STXSX GEN /N(SS2M),LB1,RF3,FFA,MF1,BB1 MIR->OPR 781 STXSP GEN /N(SS3M),RF3,24(ADDR) ADDR->OPR 782 EJEC 783 * SEARCH A TABLE FOR THE VALUE IN R0. 784 * 785 XLATE1 GEN /N(XLATE2),SF1,IM5,RF1,AA1 OF(ALU),R1->P 786 XLATE2 GEN /N(XLATE3),SF1,IM9,RF4,FF3,MF1, OF(P),INCP,0->R1 787 CWR1,AA1 788 XLATE3 GEN /N(XLATE4),LB1,RF2,FF6,BB1,SH1 -MIR-1->SC 789 MORG 4 790 XLATE5 GEN /P(VSS3M),SF2,GF4,IM4,RF1,CF3, IF(ALU),W2+1->P 791 C24(W2) 792 XLATE4 GEN /T(XLATE6,XLATE5),TF3,GFC,IM1, WAIT(M),INC SC,R1+1->R1 793 CRF5,CF3,WR1,AA1 794 XLATE6 GEN /N(XLATE7),GF2,LB1,FF6,CF3,BB1 R0-MIR,SAMPLE 795 XLATE7 GEN /T(XLATE4,XLATE5),TF3,SF2,GF9, CND(NO ALUZ) OF(P),INCP 796 CIM9,RF4 797 EJEC 798 * XIO INSTRUCTION PROCESSING. 799 * 800 * SENSE INTERRUPT. 801 SENSI1 GEN /N(SENSI2),LB1,FFA,MF1,WR1,24(W2) OPR->W2 802 SENSI2 GEN /N(SENSI3),FFF,WR1,24(ADDR) ADDR-1->ADDR 803 EVEN 804 SENSI3 GEN /N(SENSI4),LA2,WR1,WF1,24(W2) W2(L)->W2,ALU(15)->QS 805 SENSI5 GEN /N(SENSI6),SF1,IM6,24(ADDR) OS(ALU),ADDR->ALU 806 SENSI4 GEN /T(SENSI5,SENSI3),TF2,SF3,GFF, CND(QS)OF(ALU), 807 CIM5,CF3,WR1,24(ADDR) ADDR+1->ADDR 808 SENSI6 GEN /N(SENSI7),IM1,SH1 WAIT(M),ZERO->ALU 809 SENSI7 GEN /P(SENSI8+PAGE1),SF2,GF4,IM4,RF1, P1130+BASE->P, 810 CFF9,23(BASE),24(P1130) IF(ALU) 811 SENSI8 GEN /N(SS3M),SF1,IM8,LB1,RF4,FFA,MF1, IF(P),INCP,MIR->ACC 812 CWR1,BB1,24(ACC) 813 EJEC 814 * THE FOLLOWING STATES CANNOT BE IDENTIFIED AS BELONGING TO ANY 815 * SUBROUTINE OF SIGNIFICANT SIZE. 816 * 817 * ADDRESSES ARE (MOSTLY) IN ALPHABETICAL ORDER. 818 * 819 A2 GEN /N(SS2MS),GFA,LB1,FF9,WR1,BB1, ACC+MIR->ACC, 820 C24(ACC) SAMPLE OFL & COND 821 ADSD2 GEN /T(ADSD3,ASDODD),TF2,SF3,GF9,IM5, ADDR+1, CND OF(ALU) 822 CCF3,24(ADDR) 823 EVEN 824 ASDODD GEN /N(ADSD3),IM1 WAIT(MEM) 825 ADSD3 GEN /F(AD4),2(2),FSF,IM1,LB1,FFA,MF1, FS(12), 826 CWR1,BB1,24(W1) WAIT(MEM), MIR->W1 827 MORG 4 AD4, SD4 REF BY FSEL FROM ADSD3 828 AD4 GEN /N(AD5),GF2,LB1,FF9,WR1,BB1, EXT+MIR->EXT,SAMPLE 829 C24(EXT) 830 AD5 GEN /N(SS2MS),GFA,FF9,CF1,WR1, ACC+W1+CRY->ACC,SAMPLE 831 C23(W1),24(ACC) 832 ORG AD4+2 833 SD4 GEN /N(SD5),GF2,LB1,FF6,CF3,WR1,BB1, EXT-MIR->EXT,SAMPLE ALU 834 C24(EXT) 835 SD5 GEN /N(SD6),GFA,FF6,CF1,WR1,23(W1), ACC-W1+CRY->ACC, 836 C24(ACC) SAMPLE ALU & OVFL 837 SD6 GMSK /N(S3),LB3,RF3,FFA,MKF7FF X'800->OPR 838 AND2 GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, ACC & MIR->ACC,IBR->I, 839 CFFB,MF1,WR1,BB1,24(ACC) DECODE,EN INT, 840 * SEL & RESET INT FLAG 841 BSI2 GEN /N(BSI3),IM1,LA1,FF6,CF3,23(BASE) WAIT(MEM),P-BASE->ALU 842 BSI3 GEN /N(SS2M),SF1,IM4,RF1,CF3,24(ADDR) IF(ALU), ADDR+1 -> P 843 EOR2 GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, ACC EOR MIR -> ACC, 844 CFF6,MF1,WR1,BB1,24(ACC) IBR->I,DECODE,EN INT, 845 * SEL&RESET INT FLAG 846 LDA2 GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, MIR->ACC,IBR->I,DECODE, 847 CFFA,MF1,WR1,BB1,24(ACC) EN INT, SEL&RST INT FLG 848 LDD2 GEN /T(LDD3,LDDODD),TF2,SF3,GF9,IM5, ADDR+1, CND OF(ALU) 849 CCF3,24(ADDR) 850 EVEN 851 LDDODD GEN /N(LDD3),IM1 WAIT(MEM) 852 LDD3 GEN /N(LDD4),IM1,LB1,FFA,MF1,WR1,BB1, WAIT(MEM), MIR->ACC 853 C24(ACC) 854 LDD4 GEN /N(SS3M),SF1,IM8,RF4,LB1,FFA, INCP,IF(P),MIR->EXT 855 CMF1,WR1,BB1,24(EXT) 856 EVEN LDSRC,LDSSC REF BY FSEL 857 LDSRC GEN /F(LDSRO),2(1),FS4,GF2,FF3 RST CRY, SAMPLE, FS(0) 858 LDSSC GEN /F(LDSRO),2(1),FS4,GF2,FF3,CF3 SET CRY, SAMPLE, FS(0) 859 EVEN LDSRO,LDSSO REF BY FSEL 860 LDSRO GEN /N(LDSX),SF1,GF4,IM8,RF4 RESET OVFL, INCP, IF(P) 861 LDSSO GEN /N(LDSX),SF1,GF2,IM8,RF4 SET OVFL, INCP, IF(P) 862 LDSX GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, STATUS->STAT,IBR->I, 863 CFFA,MF1,WR1,BB3,24(STAT) DECODE, EN INTS, 864 * SEL & RESET INT FLAG 865 OR2 GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, ACC OR MIR->ACC,IBR->I, 866 CFF1,WR1,BB1,24(ACC) DECODE, EN INT, 867 * SEL & RST INT FLG 868 S2 GEN /N(S3),GFA,LB1,FF6,CF3,WR1,BB1, ACC-MIR->ACC, 869 C24(ACC) SAMPLE ALU & OVFL 870 S3 GEN /N(S4),SF1,IM8,LB1,RF4,FFA,MF1, INCP,IF(P),SREG->STAT 871 CWR1,BB3,24(STAT) 872 S4 GEN /N(INTBAS),1(X'F),GF5,IM6,LB1, STAT XOR OPR -> STAT, 873 CFF6,MF1,WR1,BB0,24(STAT) SEL&RST CINTF, IBR->I, 874 * ENABLE INTS, DECODE 875 STD2 GEN /N(STD3),IM1,24(ACC) WAIT(MEM),ACC->ALU 876 STD3 GMSK /N(STD4),GF2,LB3,FF7,MK1,16(ADDR) ADDR & 1, SAMPLE 877 STD4 GEN /T(STDEVN,SS2M),TF2,SF3,GF9,IM6, ADDR+1, 878 CCF3,24(ADDR) CND OS(ALU) (ALUZ) 879 STO2 GEN /N(SS3M),SF1,IM8,RF4,24(ACC) INCP,IF(P),ACC->ALU 880 XIO2 GEN /N(E620MV),LB1,FF7,MF1,WR1,24(ADDR) MAKE ADDRESS EVEN 881 EJEC 882 * STEP KEY DETECT. ENTER 620 HALT LOOP 883 * 884 STEP1 GEN /N(STEP2),FF6,CF3,WR1,23(BASE), P1130-BASE->P1130 885 C24(P1130) 886 STEP2 GEN /N(STEP3),RF1,24(P620) P620->P 887 STEP3 GMSK /N(STEP4),RF3,LB3,FFA,MKFFFD 2->OPERAND 888 STEP4 GEN /P(VSTEP),IM3,LB1,FFA,MF1,WR1,AA2 OPERAND->R2 889 ORG X'1FF STEP INTERRUPTS TO HERE 890 STEP GEN /N(STEP1),LA1,RF1,FFF,WR1, P-1 ->P,P1130 891 C24(P1130) 892 EJEC 893 END 894