COMP EQU X'F000 USED TO COMPLEMENT NEXT 4 DEFINITIONS. A14A13 EQU X'8000 ENABLE DECODER A BITS 14 AND 13. I74 EQU X'4000 ENABLE INSTRUCTION REGISTER BITS 7-4. I30 EQU X'2000 ENABLE INSTRUCTION REGISTER BITS 3-0. A84 EQU X'1000 ENABLE DECODER A BITS 8-4. O4 EQU X'0800 EXTERNAL SIGNAL FOR INR. A80 EQU X'0400 ENABLE BITS 8-0 OF DECODER A IF * A14A13 OR A84 ARE USED. IOBIT EQU X'0200 EXTERNAL SIGNAL FOR I/O. SWA EQU COMP-A84 FOR SINGLE WORD ADDRESSING. SWANS EQU X'182 BASE ADDRESS FOR SWA, NO STORE. SWASTO EQU X'181 BASE ADDRESS FOR SWA, STORE. IO EQU X'180 I/O INSTRUCTIONS. * * CONTENTS OF THE DECODER B WORDS. * * B0 EQU COMP-A14A13+A80 NOT SINGLE WORD ADDRESSING B1 EQU SWA+SWANS LOAD A B2 EQU SWA+SWANS LOAD B B3 EQU SWA+SWANS LOAD X B4 EQU SWA+O4+SWANS INR B5 EQU SWA+SWASTO STORE A B6 EQU SWA+SWASTO STORE B B7 EQU SWA+SWASTO STORE X B8 EQU SWA+IOBIT+IO I/O INSTRUCTIONS B9 EQU SWA+SWANS INCLUSIVE OR BA EQU SWA+SWANS ADD BB EQU SWA+SWANS EXCLUSIVE OR BC EQU SWA+SWANS SUBTRACT BD EQU SWA+SWANS AND BE EQU SWA+SWANS MULTIPLY BF EQU SWA+SWANS DIVIDE * DCS FORM 16,16,16,16 * * GENERATE THE DATA * DCS 1(B0),2(B1),3(B2),4(B3) DCS 1(B4),2(B5),3(B6),4(B7) DCS 1(B8),2(B9),3(BA),4(BB) DCS 1(BC),2(BD),3(BE),4(BF) END /LOAD,MIDAS . I/O CONTROL STORE * I/O CONTROL STORE CONTENTS FOR 620 AND 1130 EMULATION. IOCS FORM 16,16,16,16 * * ORG 0 IDLE ENTERED VIA RESET KEY. IOCS 1(O'000210),2(O'000000),3(O'000000),4(O'000000) * * ORG 4 SEN, EXC, EXCA IOCS 1(O'030210),2(O'000210),3(O'004210),4(O'006210) IOCS 1(O'006211),2(O'000000),3(O'000210),4(O'000000) * * ORG X'0C PROGRAMMED INPUT AND HALT LOOP IOCS 1(O'030210),2(O'000210),3(O'004210),4(O'006210) IOCS 1(O'006210),2(O'140210),3(O'140610),4(O'170600) IOCS 1(O'000000),2(O'000210) * * ORG X'1C PROGRAMMED OUTPUT AND HALT LOOP IOCS 1(O'030200),2(O'000210),3(O'004210),4(O'006210) IOCS 1(O'036210),2(O'004210),3(O'004610),4(O'004610) IOCS 1(O'000000),2(O'000210) * * ORG X'40 DMA OUTPUT IOCS 1(O'140203),2(O'142200),3(O'172200),4(O'000346) IOCS 1(O'130306),2(O'004200),3(O'004600),4(O'004602) IOCS 1(O'000000),2(O'000210) * * ORG X'50 DMA INPUT IOCS 1(O'140203),2(O'142200),3(O'172200),4(O'000200) IOCS 1(O'000200),2(O'140346),3(O'140200),4(O'140706) IOCS 1(O'140602),2(O'000000),3(O'000210) * * ORG X'60 HIGH SPEED DMA INPUT IOCS 1(O'172343),2(O'000200),3(O'134703),4(O'004602) IOCS 1(O'000000),2(O'000210) * * ORG X'70 HIGH SPEED DMA OUTPUT IOCS 1(O'172343),2(O'140200),3(O'140703),4(O'000202) IOCS 1(O'000000),2(O'000210) * * ORG X'DC INTERRUPT IOCS 1(O'140213),2(O'142210),3(O'172200),4(O'000300) IOCS 1(O'000600),2(O'000602),3(O'000200),4(O'000200) IOCS 1(O'000200),2(O'000000),3(O'000210) * * ORG X'F0 UNKNOWN FUNCTION IOCS 1(O'140213),2(O'142210),3(O'172200),4(O'000300) IOCS 1(O'000600),2(O'000602),3(O'000200),4(O'000200) IOCS 1(O'000200),2(O'000000),3(O'000210) END