; =========================================================================
; IBM 1401 AUTOMATED LOGIC DIAGRAM RECONSTRUCTION: SHEET 31.08.11.2
; =========================================================================

Page, logic=31.08.11.2, machine=1401, number=729065, title="PROGRAM SKIP LATCH"

; =========================================================================
; SMS HARDWARE BLOCK LOGIC (TOP HALF MATRIX SEGMENTS)
; Symbols corrected to alphanumeric bare names. Titles bounded to <= 10 chars.
; =========================================================================

2B: Block, symbol="AO", func="BA", mode=U.U, &
          frame=01, module=B, ec=A, gate=2, column=D, row=08, card="HH", block=01, &
          title="NOT UNIT"

3B: Block, symbol="A", func="BA", mode=U.U, &
          frame=01, module=B, ec=A, gate=2, column=E, row=14, card="ZN", block=02, &
          title="I-A STAR"

4B: Block, symbol="AO", func="BA", mode=U.U, &
          frame=01, module=B, ec=A, gate=2, column=C, row=01, card="VU", block=03, &
          title="SEL UNIT"

5A: Block, symbol="AO", func="BA", mode=U.U, &
          frame=01, module=B, ec=A, gate=2, column=C, row=15, card="WW", block=04, &
          title="I-O OPS"

; =========================================================================
; MAIN COUPLING LOGIC BLOCK: THE PROGRAM SKIP LATCH (ROW SEGMENT E)
; =========================================================================

5E: Block, symbol="CRZV", func="BA", mode=U.U, &
          frame=01, module=B, ec=E, gate=2, column=D, row=12, card="CH", block=01, &
          title="PROG SKIP"

6E: Block, symbol="CRZV", func="BA", mode=U.U, &
          frame=01, module=B, ec=E, gate=2, column=D, row=14, card="CH", block=02, &
          title="SKIP"

; =========================================================================
; SIGNAL BOUNDARY INPUT LINES (LEFT EDGE CONNECTORS)
; =========================================================================

IB1: Input, level=+U, logic=31.09.11.2, text="NOT UNIT"
IB2: Input, level=-T, logic=35.16.31.2, text="REG BLANK"
IC1: Input, level=-T, logic=31.31.21.2, text="I RING 5"
ID1: Input, level=+U, logic=31.05.11.2, text="NOT NOT OP"
IE1: Input, level=+U, logic=31.01.11.2, text="TIME 030-060"

; =========================================================================
; SIGNAL BOUNDARY OUTPUT LINES (RIGHT EDGE CONNECTORS)
; =========================================================================

OB1: Output, level=-T, logic=32.44.31.2, text="NOT UNIT"
OB2: Output, level=+U, logic=31.07.11.2, text="UNCOND XFER"

; =========================================================================
; NET ROUTING MATRIX LINES
; =========================================================================

Line, from=IB1, to=2B.1.A.R
Line, from=IB2, to=2B.2.B.R
Line, from=IC1, to=3B.1.A.R

D1: Dot, at=4C.3.5

Line, from=2B.9.F, to=D1.R
Line, from=3B.9.F, to=D1.R
Line, from=D1, to=5E.1.A.R

Line, from=5E.9.G, to=OB1.R
Line, from=6E.9.G, to=OB2.R

; =========================================================================
; SHEET METADATA, DOCUMENT NOTES, AND EC HISTORY BLOCKS
; =========================================================================

Comment, text=["NOTE: WHEN A SIGNAL IS PRECEDED BY", &
               "AN ASTERISK, ITS EXPANSION INDICATES", &
               "CABLE WIRING FOR REMOTE RECYCLE CONTROL"]

EC, date="07-02-63", number=1713, tag=D
EC, date="05-03-63", number=1771, tag=E