# P=page
# bk drawing# logic#     FR_CH MFI  "title"                  "feature"
P  7 761264   B9.40.12.1 00xc  M0   "Error stop read gating" "TAU 9"

# L=logic
# ColRow Symbol out    loc
#    type     in    ec    sub  ["title"] [*{a-h,s-z}pin/tie]...
L 3b dhc- i    y  y  c b07 01
L 4b dfj- R-12 .  .  f c10 01
L 5b dhc- i    y  y  c b07 02
L 6b dfj- r-12 .  .  f c10 02

l 3c dhc- i    y  y  c c11 03
l 4c dfj- r-12 .  .  f c10 03
l 5c dhc- i    y  y  c c11 04
l 6c dfj- r-12 .  .  f c10 04

l 3d dhc- i    y  y  c c11 01
l 4d dfj- r-12 .  .  f c10 04
l 5d dhc- i    y  y  c c11 02
l 6d dfj- r-12 .  .  f c10 06

L 3e dhc- i    y  y  c c11 03
L 4e dfj- R-12 .  .  f c10 07
L 5e dhc- i    y  y  c c11 04
L 6e dfj- r-12 .  .  f c10 08

l 3f dhc- i    y  y  c c11 05
l 4f dfj- r-12 .  .  f c10 09
l 5f dhc- i    y  y  c c11 06
l 6f dfj- r-12 .  .  f c10 10

l 3g dhc- i    y  y  c c17 01
l 4g dfj- r-12 .  .  f c10 11
l 5g dhc- i    y  y  c c17 02
l 6g dfj- r-12 .  .  f c10 12

l 3h dhc- i    y  y  c c17 03
l 4h dfj- r-12 .  .  f a17 09
l 5h dhc- i    y  y  c c17 04
l 6h dfj- r-12 .  .  f a17 10

l 3j dhc- i    y  y  c b07 06
l 4j dfj- r-12 .  .  f a17 02
l 5j dhc- i    y  y  c f11 02

# rows:
#  01- 03 heading
#  03- 21 A
#  22- 39 B
#  40- 57 C
#  58- 75 D
#  76- 93 E
#  94-101 F
# 102-119 G
# 120-137 H
# 138-155 J
# 156-173 notes 1
# 174-191 notes 2

# Within a logic box (A-H,J)
# wiring    1-2
# Title     3
# top line  4 A J
# type      5 B K
# MFI       6 C L
# in out    7 D M
# llle      8 E N
# llll      9 F P
# card/cap 10 G Q
# note     11 H R
# coord    12
# wiring   13-18

# Columns
# 01-17   title or ^logic + --*n or -*nn
# 18-34   2
# 35-51   3
# 52-68   4
# 69-85   5
# 86-102  6
# 103-120 title or *n-- or *nn- + logic^

# Within a logic box
#   1-4 ----
#   5-6 pin,tie
#  7-12 Box
# 13-14 pin,tie
# 15-17 ---

# I=input edge
#    row is where logic indicator appears, titles above
#  # row Logic#     ["title 1" ["title 2"]] [*note]
I 01 b06 b9.40.10.1 "-y hi clip 1" "bit"
i 02 b15 b9.40.10.1 "-y lo clip 1" "bit"
i 03 c06 b9.40.10.1 "-y hi clip 2" "bit"
i 04 c15 b9.40.10.1 "-y lo clip 2" "bit"
I 05 d06 b9.40.10.1 "-y hi clip 4" "bit"
i 06 d15 b9.40.10.1 "-y lo clip 4" "bit"
i 07 e06 b9.40.10.1 "-y hi clip 8" "bit"
i 08 e15 b9.40.10.1 "-y lo clip 8" "bit"
i 09 f06 b9.40.10.1 "-y hi clip a" "bit"
i 10 f15 b9.40.10.1 "-y lo clip a" "bit"
I 11 g06 b9.40.10.1 "-y hi clip b" "bit"
i 12 g15 b9.40.10.1 "-y lo clip b" "bit"
i 13 h06 b9.40.10.1 "-y hi clip c" "bit"
i 14 h15 b9.40.10.1 "-y lo clip c" "bit"
i 15 j06 b9.60.20.1 "+y read cond" ""     *1

# O=output edge
#    row is where logic indicator appears, titles above
#  # row Logic#     ["title 1" ["title 2"]] [*note]
o 01 a15 b9.40.20.1 "+y hi chan 1" "bit"
o 02 a18 b9.40.60.1
o 03 b06 b9.40.20.1 "+y lo chan 1" "bit"
o 04 b09 b9.40.60.1
o 05 b15 b9.40.20.1 "+y hi chan 2" "bit"
o 06 b18 b9.40.60.1
o 07 c06 b9.40.20.1 "+y lo chan 2" "bit"
o 08 c09 b9.40.60.1
o 09 c15 b9.40.21.1 "+y hi chan 4" "bit"
o 10 c18 b9.40.60.1
o 11 d06 b9.40.21.1 "+y lo chan 4" "bit"
o 12 d09 b9.40.60.1
o 13 d15 b9.40.21.1 "+y hi chan 8" "bit"
o 14 d18 b9.40.60.1
o 15 e06 b9.40.21.1 "+y lo chan 8" "bit"
o 16 e09 b9.40.60.1
o 17 e15 b9.40.22.1 "+y hi chan a" "bit"
o 18 e18 b9.40.60.1
o 19 f06 b9.40.22.1 "+y lo chan a" "bit"
o 20 f09 b9.40.60.1
o 21 f15 b9.40.22.1 "+y hi chan b" "bit"
o 22 f18 b9.40.60.1
o 23 g06 b9.40.22.1 "+y lo chan b" "bit"
o 24 g09 b9.40.60.1
o 25 g15 b9.40.23.1 "+y hi chan c" "bit"
o 26 g18 b9.40.60.1
o 27 h06 b9.40.23.1 "+y lo chan c" "bit"
o 28 h09 b9.40.60.1
o 29 j09 b9.40.10.1 "+v rd cond gate" "on final amps"

# C=connection
# A [B]... B
# A = Ixx (xx = input number)
#     CRrr[*]{pin}[tie] C=2-6 R=a-h,j rr=01-18
#     .CRccrr C=2-6 R=a-h,j cc=01-15 rr=01-17 (dot)
# B = Oxx (xx = output number ) (only the last one)
#     {ud}{a-f}{01-18} up or down to row {a-f}{01-18}
#     {lr}{1-6}{01-17} left or right to column {1-6}{01-17}
#     C{pin}[tie] C=2-6
#     . (dot)

c i01     3r
c 3b05*a  r316 . 4a
c .3b0516 ua18 . ua15 o01
d .3a1816 o02

c i02     r503 ub10 cp
c 5b15*c  r316 . 6b
c .5b0516 ua17 r617 db06 . o03
c .6b0617 db08 o04

-- old style from here

# C=connection
#   A B [via]...
# A or B = Ixx (only A)
#          cr{a-r}[*]{pin}{tie} where a-h are in, j-r are output (no O)
#                               * only on A
#          Oxx (only B)
#          #{a-f}{01-18}{01-17} for logic box, row in box, column in box
# via =    {ud}{a-f}{01-18} up or down to row {a-f}{01-18}
#          {lr}{1-6}{01-17} left or right to column {1-6}{01-17}

c 5b0517 o04    ua18 r617 db09
c 6b0617 o03

c i03    3ccg
c 3ck*f  6b1617 r403 ub16
c 6b1617 o05    ub15
c 6b1617 o06    db18
c 4b1604 4cbc   dc05
c i04    5cgq   r504
c 5cj*b  6cbd
c 5c0517 o08    ub17 r616 dc09
c 6c0616 O07

c i05    3dcr
c 3dk*a  6c1617 r403 uc16
c 6c1617 o09    uc15
c 6c1617 o10    dc18
c 4c1604 4dbe   dd05
c i06    5dgp   r504
c 5dj*c  6dbf
c 5d0517 o12    uc17 r616 dd09
c 6d0616 o11

c i07    3ecg
c 3ek*d  6d1617 r403 ud16
c 6d1617 o13    ud15
c 6d1617 o14    dd18
c 4d1604 4ebe   de05
c i08    5egq   r504
c 5ej*c  6ebh
c 5e0517 o16    ud17 r616 de09
c 6e0616 o15

c i09    3fce
c 3fk*d  6e1617 r403 ue16
c 6e1617 o17    ue15
c 6e1617 o18    de18
c 4e1604 4fbe   df05
c i10    5fgh   r504
c 5fj*l  6fbf
c 5f0517 o20    ue17 r616 df09
c 6f0616 o19

#n note# where
n *1 00xcc01p

#* comment, blanks significant
*     1401  1410
*00xc 02b4  14d6