1401-HL Project Status
Project File:	1401-HL.ise	Implementation State:	Synthesized
Module Name:	andgate	Errors:	No Errors
Target Device:	xc5vlx30-3ff324	Warnings:	No Warnings
Product Version:	ISE 11.1	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

Device Utilization Summary (estimated values)				[-]
Logic Utilization	Used	Available	Utilization
Number of Slice LUTs	1	19200	0%
Number of fully used LUT-FF pairs	0	1	0%
Number of bonded IOBs	3	220	1%

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Oct 2 11:38:30 2009	0	0	0
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 10/09/2009 - 20:29:36