A_Reg_True_Complement Project Status (12/16/2009 - 19:26:51)
Project File: A_Reg_True_Complement.ise Implementation State: Synthesized (Failed)
Module Name: A_Reg_True_Complement
  • Errors:
 X 2 Errors
Target Device: xc5vlx30-3ff324
  • Warnings:
 No Warnings
Product Version:ISE 11.1
  • Routing Results:
  
Design Goal: Balanced
  • Timing Constraints:
  
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 16 19:26:49 2009X 2 Errors00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/16/2009 - 19:26:51