A_Reg_True_Complement Project Status
Project File:	A_Reg_True_Complement.ise	Implementation State:	New (Failed)
Module Name:	Reg_Translator	Errors:
Target Device:	xc5vlx30-3ff324	Warnings:
Product Version:	ISE 11.1	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 12/16/2009 - 19:26:51