Release 11.1 - xst L.33 (lin) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to /users/vsnyder/1401/docs/ALD/progs/A_Reg_True_Complement/xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.06 secs --> Parameter xsthdpdir set to /users/vsnyder/1401/docs/ALD/progs/A_Reg_True_Complement/xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.06 secs --> ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "/../../../../../../../../../users/vsnyder/1401/verilog/Reg_Translator.v" in library work Compiling verilog file "/../../../../../../../../../users/vsnyder/1401/docs/ALD/progs/A_Reg_True_Complement/A_Reg_True_Complement.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"Reg_True_Complement.prj"> succeeded. Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.06 secs --> Total memory usage is 118808 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)