flash Project Status | |||
Project File: | flash.ise | Implementation State: | Synthesized |
Module Name: | flash |
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No Errors |
Target Device: | xc4vlx15-12sf363 |
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No Warnings |
Product Version: | ISE 11.1 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 11 | 6144 | 0% | |
Number of Slice Flip Flops | 14 | 12288 | 0% | |
Number of 4 input LUTs | 18 | 12288 | 0% | |
Number of bonded IOBs | 18 | 240 | 7% | |
Number of GCLKs | 2 | 32 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Dec 16 19:28:04 2009 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |