flash Project Status
Project File: flash.ise Implementation State: Synthesized
Module Name: flash
  • Errors:
No Errors
Target Device: xc4vlx15-12sf363
  • Warnings:
No Warnings
Product Version:ISE 11.1
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 11 6144 0%
Number of Slice Flip Flops 14 12288 0%
Number of 4 input LUTs 18 12288 0%
Number of bonded IOBs 18 240 7%
Number of GCLKs 2 32 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 16 19:28:04 2009000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/17/2009 - 10:57:49