qui_bi Project Status (12/16/2009 - 19:02:48)
Project File: qui_bi.ise Implementation State: Synthesized
Module Name: Reg_Translator
  • Errors:
 No Errors
Target Device: xc5vlx30-3ff324
  • Warnings:
 No Warnings
Product Version:ISE 11.1
  • Routing Results:
  
Design Goal: Balanced
  • Timing Constraints:
  
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 5 19200 0%
Number of fully used LUT-FF pairs 0 5 0%
Number of bonded IOBs 13 220 5%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 16 19:02:48 2009000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/16/2009 - 19:02:48