Release 11.1 Map L.33 (lin) Xilinx Mapping Report File for Design 'Reg_True_Complement' Design Information ------------------ Command Line : map -ise qui_bi.ise -intstyle ise -p xc5vlx30-ff324-3 -w -logic_opt off -ol std -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o Reg_True_Complement_map.ncd Reg_True_Complement.ngd Reg_True_Complement.pcf Target Device : xc5vlx30 Target Package : ff324 Target Speed : -3 Mapper Version : virtex5 -- $Revision: 1.51 $ Mapped Date : Wed Dec 16 19:00:29 2009 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice LUTs: 6 out of 19,200 1% Number used as logic: 6 out of 19,200 1% Number using O6 output only: 6 Slice Logic Distribution: Number of occupied Slices: 5 out of 4,800 1% Number of occupied SLICEMs: 0 out of 1,280 0% Number of LUT Flip Flop pairs used: 6 Number with an unused Flip Flop: 6 out of 6 100% Number with an unused LUT: 0 out of 6 0% Number of fully used LUT-FF pairs: 0 out of 6 0% Number of slice register sites lost to control set restrictions: 0 out of 19,200 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 16 out of 220 7% Specific Feature Utilization: Average Fanout of Non-Clock Nets: 2.07 Peak Memory Usage: 310 MB Total REAL time to MAP completion: 17 secs Total CPU time to MAP completion: 11 secs Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Control Set Information Section 14 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). INFO:Pack:1650 - Map created a placed design. Section 4 - Removed Logic Summary --------------------------------- Section 5 - Removed Logic ------------------------- Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | Comp | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_1 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_B0_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_B1_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_Not_1 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q0 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q2 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q4 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q6 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q8 | IOB | INPUT | LVCMOS25 | | | | | | | | Reg_Q0_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_Q2_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_Q4_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_Q6_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | Reg_Q8_TC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | True | IOB | INPUT | LVCMOS25 | | | | | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- A logic-level (pre-route) timing report can be generated by using Xilinx static timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the mapped NCD and PCF files. Please note that this timing report will be generated using estimated delay information. For accurate numbers, please generate a timing report with the post Place and Route NCD file. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference Manual; for more information about TRCE, consult the Xilinx Command Line Tools User Guide "TRACE" chapter. Section 12 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Control Set Information ------------------------------------ Use the "-detail" map option to print out Control Set Information. Section 14 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.