qui_bi Project Status (12/16/2009 - 19:02:48)
Project File:	qui_bi.ise	Implementation State:	Placed and Routed
Module Name:	Reg_True_Complement	Errors:	No Errors
Target Device:	xc5vlx30-3ff324	Warnings:	1 Warning
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Slice Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice LUTs	6	19,200	1%
Number used as logic	6	19,200	1%
Number using O6 output only	6
Number of occupied Slices	5	4,800	1%
Number of occupied SLICEMs	0	1,280	0%
Number of LUT Flip Flop pairs used	6
Number with an unused Flip Flop	6	6	100%
Number with an unused LUT	0	6	0%
Number of fully used LUT-FF pairs	0	6	0%
Number of slice register sites lost         to control set restrictions	0	19,200	0%
Number of bonded IOBs	16	220	7%
Average Fanout of Non-Clock Nets	2.07

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report	Current	Wed Dec 16 19:00:26 2009	0	0	0
Map Report	Current	Wed Dec 16 19:00:47 2009	0	0	6 Infos
Place and Route Report	Current	Wed Dec 16 19:01:01 2009	0	1 Warning	1 Info
Power Report
Post-PAR Static Timing Report	Current	Wed Dec 16 19:01:10 2009	0	0	3 Infos
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 12/16/2009 - 19:02:48