test Project Status (10/01/2009 - 20:11:28)
Project File: test.ise Implementation State: Synthesized
Module Name: mux2
  • Errors:
 No Errors
Target Device: xa95*xl-**
  • Warnings:
 No Warnings
Product Version:ISE 11.1
  • Routing Results:
  
Design Goal: Balanced
  • Timing Constraints:
  
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Oct 1 20:10:17 2009000
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 10/02/2009 - 11:09:29