Set up the overlay loader in phase zero to load from cards, tape with one phase per block, or Autocoder tape with one field per record. Revised the tape error handler to be usable after any read by making it a subroutine that backs up its return address by thirteen characters, and clearing its error counter before it exits instead of requiring to clear it before the read. So as to allow phase zero fit in the same space, the "clear core" at the end of each phase was moved from the monitor (MONTOR in Gary's code) to an overlay after each phase. Because I had reverse-engineered the V3M0 and V3M4 tapes into one file per phase before Gary found the listings he thought had been lost when he retired, each phase didn't know, from Autocoder, the load and entry addresses for the next phase. So as not to need to find addresses in each phase and put them manually into the previous one, I put the loader from each phase into an overlay before the phase, which uses the error handler in phase zero. The result is that the loader in phase 0 is tiny, loading from cards, or from Autocoder tape into 1, or from a tape with one phase per block into 201 to load the phase's "load me" overlay, which then loads the phase. If loading from an Autocoder tape, each overlay's bootstrap record is loaded into 1-79. If loading from cards, each overlay is loaded using "R 40." All of the phases are shorter by not having their "clear me" code, the phase ID of the next phase (to be copied to 110) and not adjusting the monitor for the next phases load and entry addresses, but they still have the same ORG addresses even though Phase zero is shorter (ends at 804 instead of 837). When tape blocks are used, instead of one-field-per-record Autocoder tapes, some phases are too big to fit through the CHM TAU emulator. Those phases are split by putting another "load me" overlay in the middle, with the XFR at the first half entering the loader in phase zero, and the XFR at the end entering at the original place. Labels in each phase that are referenced in another phase are identified by putting an asterisk in column 1 of the "page number" field. A post processor that looks for that asterisk in the listing creates an EQU for that label, with the address from the listing, and creates a macro of a specified name for all of that phase's externally accessible labels. Inserted that macro into files that need it. The post processor is written in Fortran, but could have been written in Autocoder. Phase 12, DIMEN TWO, referred to addresses in the runtime format routines, with a warning in comments to change them, and their decimal equivalents, if the runtime was reassembled,. The asterisk method and the post processor were used to get those addresses automagially into DIMEN TWO from phase-54B and phase-54CD. Removed the need for their decimal equivalents by revising the convert-3-to-5 routine (significantly shortening it), and using it at the beginning as well as the other two places. Phase 12 is now 2158 characters instead of 2273 characters. Phase 35 was eliminated because it never did anything more than load phase 36. Phase 53R was eliminated by putting "load me" macros in the right places. Set up the "load me" macro to be able to look at a flag and skip loading a phase. Phase 54A uses this to load or skip phases 54B, C and D, and phase 61 uses this to load or skip phase 62.. The overlay to clear phase 54A is in phase 55 because phase 54A skips or loads phases 54BCD. The overlay to clear phase 61 is in phase 62 because it either skips or loads phase 62. Phase 58 was considerably simplified by using skip-a-deck and read-a-card subroutines to skip or punch parts of phase 59. There's a flow chart of Gary's original code in 5054.obj (a "tgif" file) and 5054.pdf. Phases 52BC and 58 read card images, and expect to still have the word marks set for running from the bootstrap loader. When loading from an Autocoder "tape." that's messed up, so I had to restore them. If the optional sixth argument to the "load next phase" macro is present, it causes a stop. That's not used in any of the phases now, but I left the code in the macro in case I need to do it again. I used this during debugging. The compiler-gen4 program can build a tape from a deck that contains a program, provided the PARAM card does not have L in column 40 or B in column 68. ============================================== Sense switches: B: If a deck is requested on the parameter card, print it too. C: Give a snapshot dump after each phase, except: D: Give s anapshot dump after phases 16, 17, 20, 27, 30, and 50A, and E: Give a snapshot dump after phases 12, 13, 31, and 46. F: Only dump the phase ID in a snapshot. G: Stop after each snapshot. The snapshot is included in the generated program but I don't know how to get to it. None of the sense switches turn it on. Maybe it's there so you can remove the "end" card, or change it to start at 333, to get a core dump before running the program. It doesn't "return" properly. As the "load next phase" macro is currently set up, SS G also causes a branch to a halt in the "load next phase" macro. So if you select snapshot dumps, you get two halts per phase. ============================================== Blocks on the tape (not quite right anymore) 1. Phase 0 -- tables, snapshot dump, loader, setup 2. Load phases 1 & 2 3. Phases 1 & 2 -- Parameter card, load program into core. 4. Load part 2 of Phases 1 & 2 5. Part 2 of Phases 1 & 2 6. Clear Phases 1 & 2 7. Load Phase 3 -- Scanner 8. Phase 3 -- Scanner 9 Clear Phase 3 10. Load phase 4 -- Sorter One 11. Phase 4 -- Sorter One 12. Clear phase 4 13. Load Phase 5 -- Sorter Two 14. Phase 5 -- Sorter Two 15. Clear Phase 5 16. Load Phase 6 -- Sorter Tri 17. Phase 6 -- Sorter Tri 18. Clear phase 6 19. Load Phase 7 -- Group Mark 20. Phase 7 -- Group Mark 21. Clear Phase 7. 22. Load Phase 8 -- Squoze 23. Phase 8 -- Squoze 24. Clear Phase 8 -- Squoze 25. Load Phase 9 -- Dimen One 26. Phase 9 -- Dimen One 27. Clear Phase 9 28. Load Phase 10 -- Equiv One 29. Phase 11 -- Equiv One 30. Clear Phase 11 31. Load Phase 11 -- Equiv Two 32. Phase 11 -- Equiv Two 33. Clear Phase 11 34. Load Phase 12 -- Dimen Two 35. Phase 12 -- Dimen Two 36. Clear Phase 12 37. Load Phase 13 -- Varbl One 38. Part 1 of Phase 13 -- Varbl One 39. Load Part 2 of Phase 13 40. Part 2 of Phase 13 41. Clear Phase 13 42. Load Phase 14 -- Varbl Two 43. Phase 14 -- Varbl Two 44. Clear Phase 14 45. Load Phase 15 -- Varbl Tri 46. Phase 15 -- Varbl Tri 47. Clear phase 15 48. Load Phase 16 -- Varbl Quad 49. Phase 16 -- Varbl Quad 50. Clear phase 16 51. Load Phase 17 -- Varbl Quin 52. Phase 17 -- Varbl Quin 53. Clear Phase 17 54. Load Phase 18 part 1 -- Const One 55. Phase 18 part 1 -- Const One 56. Load Phase 18 part 2 -- Const One 57. Phase 18 Part 2 -- Const One 58. Clear phase 18 59. Load Phase 19 -- Const Two 60. Phase 19 -- Const Two 61. Clear Phase 19 62. Load Phase 20 -- Const Tri 63. Phase 20 -- Const Tri 64. Clear Phase 20 65. Load Phase 21 -- Subscr 66. Phase 21 -- Subscr 67. Clear Phase 21 68. Load Phase 22 -- Stnum One 69. Phase 22 -- Stnum One 70. Clear Phase 22 -- Stnum One 71. Load Phase 23 -- Tamrof One 72. Phase 23 -- Tamrof One 73. Clear Phase 23 74. Load Phase 24 -- Tamrof Two 75. Phase 24 -- Tamrof Two 76. Clear Phase 24 77. Load Phase 25 -- Listr One 78. Phase 25 -- Listr One 79. Clear Phase 25 80. Load Phase 26 -- Listr Two 81. Phase 26 -- Listr Two 82. Clear Phase 26. 83. Load Phase 27 -- Listr Tri 84. Phase 27 -- Listr Tri 85. Clear Phase 27 86. Load Phase 28 -- Stnum Two 87. Phase 28 -- Stnum Two 88. Clear Phase 28 89. Load Phase 29 -- Stnum Tri 90. Phase 29 -- Stnum Tri 91. Clear Phase 29 92. Load Phase 30 -- Stnum For 93. Phase 30 -- Stnum For 94. Clear Phase 30 -- Stnum For 95. Load Phase 31 -- Stnum Fiv 96. Phase 31 -- Stnum Fiv 97. Clear Phase 31 98. Load Phase 32 -- I/O One 99. Phase 32 -- I/O One 100. Clear Phase 32 101. Load Phase 33 part 1 -- Arith One 102. Phase 33 Part 1 -- Arith One 103. Load Phase 33 part 2 -- Arith Two 104. Phase 33 Part 2 -- Arith One 105. Clear Phase 33 106. Load Phase 34 Part 1 -- Arith Two 107. Phase 34 Part 1 -- Arith Two 108. Load Phase 34 Part 2 -- Arith Two 109. Phase 34 Part 2 -- Arith Two 110. Clear Phase 34. 111. Load Phase 35 -- Arith Tri 112. Phase 35 -- Arith Tri 113. Clear Phase 35 114. Load Phase 36 Part 1 -- Arith For 115. Phase 36 Part 1 -- Arith For 116. Load Phase 36 Part 2 -- Arith For 117. Phase 36 Part 2 -- Arith For 118. Clear Phase 36 119. Load Phase 37 part 1 -- Arith Fiv 120. Phase 37 Part 1 -- Arith Fiv 121. Load Phase 37 Part 2 -- Arith Fiv 122. Phase 37 Part 2 -- Arith Fiv 123. Clear Phase 37 124. Load Phase 38 -- Arith Six 125. Phase 38 -- Arith Six 126. Clear Phase 38. 127. Load Phase 39 -- I/O Two 128. Phase 39 -- I/O Two 129. Clear Phase 39 130. Load Phase 40 -- CGOTO 131. Phase 40 -- CGOTO 132. Clear Phase 40. 133. Load Phase 41 -- GOTO 134. Phase 41 -- GOTO 135. Clear Phase 41 136. Load Phase 42 -- Stop/Pause 137. Phase 42 -- Stop/Pause 138. Clear Phase 42. 139. Load phase 43 -- Light 140. Phase 43 -- Light 141. Clear Phase 43 142. Load Phase 44 -- IFCOND 143. Phase 44 -- IFCOND 144. Clear Phase 44 145. Load Phase 45 -- Continue 146. Phase 46 -- Continue 147. Clear Phase 46 148. Load Phase 46 -- DOMSK 149. Phase 46 -- DOMSK 150. Clear Phase 46. 151. Load Phase 47 -- Resort One 152. Phase 47 -- Resort One 153. Clear Phase 47 154. Load Phase 48 -- Resort Two 155. Phase 48 -- Resort Two 156. Clear Phase 48 157. Load Phase 49 -- Resort Tri 158. Phase 49 -- Resort Tri 159. Clear Phase 49 160. Load Phase 50 -- Resort For 161. Phase 50 -- Resort For 162. Clear Phase 50 163. Load Phase 50B -- Shift CFL 164. Phase 50B -- Shift CFL 165. Clear Phase 50B 166. Load Phase 51 -- Replace 1 167. Phase 51 -- Replace 1 168. Clear Phase 51. 169. Load Phase 52A -- Load 52B&C 170. Phase 52A -- Load 52B&C 171. Clear Phase 52A 172. Load Phase 53B -- Funload B 173. Phase 53B -- Funload B 174. Load Phase 53C -- Funload C 175. Phase 53C -- Funload C 176-363. Relocatable runtime library 365. Load Phase 53S -- Snapshot 366. Phase 53S -- Snapshot 367. Load Phase 54A -- FormatPak 368. Phase 54A -- FormatPak 369. Load or skip Phase 54B -- Object time format 370. Phase 54B -- Object time format 371. Load or skip Phase 54C part 1 -- Normal format 372. Phase 54C part 1 -- Normal format 373. Load or skip Phase 54C part 2 -- Normal format 374. Phase 54C part 2 -- Normal format 375. Load or skip Phase 54D -- A conversion 376. Phase 54D -- A conversion 377. Clear phase 54A 378. Load phase 55 -- Replace 2 379. Phase 55 -- Replace 2 380. Clear Phase 55 381. Load Phase 56 -- Snapshot 382. Phase 56 -- Snapshot 383. Clear Phase 56 384. Load Phase 57 -- Condeck1 385. Phase 57 -- Condeck1 386. Clear phase 57 387. Load Phase 58 -- Condeck2 388. Phase 58 -- Condeck2 389-458 Card images of Phase 59 to punch the condensed deck 459. Clear Phase 58 460. Load Phase 60 -- Condeck3 461. Phase 60 -- Condeck3 462. Clear Phase 60 463. Load Phase 61 -- GEAUX One 464. Phase 61 -- GEAUX One 465. Load or skip Phase 61B -- Fixed XLINK routine 466. Phase 61B -- Fixed XLINK routine 467. Clear phase 61 468. Replaces the loader with Phase 62 -- GEAUX phase two 469. Phase 63 -- Arithmetic package 470. Halt (not used when we have phase 61 Functions Record 177: HJ41H094H0940 DOADR1 386 arith-v3m0.63.53 Record 179-180: H094M0J1!46MM DOADR2 394 arith-v3m0.63.53 Record 182: A000000?000_00S000 DOADR3 408 arith-v3m0.63.53 Record 184-185: H!49M0!2!14?000 DOINIT 432 arith-v3m0.63.53 Record 187-198: H094H!930!2H OBLIST 460 arith-v3m0.63.53 Record 200-206: HJ78M0!3J94SJ99 SUBSCR 561 arith-v3m0.63.53 Record 209-217: H!46M2G9250DLK61 509 phase-59 D Record 219-231: B!24924CB/42SY SINFUN 609 arith-v3m0.63.53 Record 233-242: Y2G9W84BK50 LOGF 722 arith-v3m0.63.53 Record 244-268: YK90|87DW84 EXPF 797 arith-v3m0.63.53 Record 270: Y!072G9 ABSVL 971 arith-v3m0.63.53 Record 272-273: !2G9B/34 NEGF 975 arith-v3m0.63.53 Record 275-278: ,W87H0890?0 FIXF 985 arith-v3m0.63.53 Record 280-281: )W87V!160!4 FLOT 1015 arith-v3m0.63.53 Record 283-289: VJ872G9KD2G92B2M SQRTF 1033 arith-v3m0.63.53 Record 291: User function 1 YUSER1 1081 arith-v3m0.63.53 Record 293: User function 2 etc Record 295: User function 2 Record 297: User function 4 Record 299: User function 5 Record 301: User function 6 Record 303: User function 7 Record 305: User function 8 Record 307: User function 9 Record 309: User function 10 Record 311: User function 11 Record 313: User function 12 Record 315: M!13359B337 XLINKF 1122 arith-v3m0.63.53 Record 317: T9030!4S Branch SINFUN S 1131 arith-v3m0.63.53 Record 319: T9030!4C Branch SINFUN C 1134 arith-v3m0.63.53 Record 321: T9000!4G Branch LOGFUN G 1137 arith-v3m0.63.53 Record 323: T8970! Branch XPNETL E 1140 arith-v3m0.63.53 Record 325: T8940!4T Branch ATANFN T 1143 arith-v3m0.63.53 Record 327: T8910!4A Branch ABSVAL A 1146 arith-v3m0.63.53 Record 329: T8880!4N Branch NEGTFN N 1149 arith-v3m0.63.53 Record 331: T8850!4X Branch FIXFUN X 1152 arith-v3m0.63.53 Record 333: T8820!4F Branch FLTFUN F 1155 arith-v3m0.63.53 Record 335: T8790!4Q Branch SQRTFN Q 1158 arith-v3m0.63.53 Record 337: T8760!4R Branch YUSER1 R 1161 arith-v3m0.63.53 Record 339: T8730!4U etc Record 341: T8700!4P Record 343: T8670!4W Record 345: T8640!4Y Record 347: T8610!4Z Record 349: T8580!4J Record 351: T8550!4K Record 353: T8520!4L Record 355: T8490!4M Record 357: T8460!4D Record 359: T8430!4H Record 361: T8400!4I Branch XLINKS I 1200 arith-v3m0.63.53