module A_Reg_True_Complement ( input True, Comp, A_Reg_1_From_Calc, A_Reg_Not_1_From_Calc, A_Reg_1, A_Reg_2, A_Reg_4, A_Reg_8, A_Reg_Not_1, A_Reg_Not_2, A_Reg_Not_4, A_Reg_Not_8, A_Reg_Q0_From_Calc, A_Reg_Q2_From_Calc, A_Reg_Q4_From_Calc, A_Reg_Q6_From_Calc, A_Reg_Q8_From_Calc, output A_Reg_B0_TC, A_Reg_B1_TC, A_Reg_Q0, A_Reg_Q2, A_Reg_Q4, A_Reg_Q6, A_Reg_Q8, A_Reg_Q0_TC, A_Reg_Q2_TC, A_Reg_Q4_TC, A_Reg_Q6_TC, A_Reg_Q8_TC ); // Fig 37, Drawing 723832 Reg_Translator T_A ( A_Reg_1, A_Reg_2, A_Reg_4, A_Reg_8, A_Reg_Not_1, A_Reg_Not_2, A_Reg_Not_4, A_Reg_Not_8, A_Reg_Q0_From_Calc, A_Reg_Q2_From_Calc, A_Reg_Q4_From_Calc, A_Reg_Q6_From_Calc, A_Reg_Q8_From_Calc, A_Reg_Q0, A_Reg_Q2, A_Reg_Q4, A_Reg_Q6, A_Reg_Q8 ); Reg_True_Complement RTC_A ( True, Comp, A_Reg_1_From_Calc | A_Reg_1, A_Reg_Not_1_From_Calc | A_Reg_Not_1, A_Reg_Q0, A_Reg_Q2, A_Reg_Q4, A_Reg_Q6, A_Reg_Q8, A_Reg_B0_TC, A_Reg_B1_TC, A_Reg_Q0_TC, A_Reg_Q2_TC, A_Reg_Q4_TC, A_Reg_Q6_TC, A_Reg_Q8_TC ); endmodule