module Binary_Adder ( input Carry, Not_Carry, A_Reg_B0_T_C, A_Reg_B1_T_C, B_Reg_1, B_Reg_Not_1, output Adder_B0, Adder_B1, Binary_Carry, Not_Binary_Carry ); // Fig 37, Drawing 723832 wire W1, W2; assign W1 = ( A_Reg_B0_T_C & B_Reg_1 ) | ( A_Reg_B1_T_C & B_Reg_Not_1 ); assign W2 = ( A_Reg_B0_T_C & B_Reg_Not_1 ) | ( A_Reg_B1_T_C & B_Reg_1 ); assign Adder_B0 = ( Carry & W1) | ( Not_Carry & W2 ); assign Adder_B1 = ( Not_Carry & W1) | ( Carry & W2 ); assign Binary_Carry = ( A_Reg_B1_T_C & B_Reg_1) | ( Carry & W1 ); assign Not_Binary_Carry = ( A_Reg_B0_T_C & B_Reg_Not_1 ) | ( Not_Carry & W1 ); endmodule