Release 11.1 - xst L.33 (lin) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> Reading design: Dwg_723832.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Dwg_723832.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "Dwg_723832" Output Format : NGC Target Device : Automotive 9500XL ---- Source Options Top Module Name : Dwg_723832 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Library Search Order : Dwg_723832.lso Keep Hierarchy : YES Netlist Hierarchy : as_optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "Mux2_TC.v" in library work Compiling verilog file "Reg_True_Complement.v" in library work Module compiled Compiling verilog file "Reg_Translator.v" in library work Module compiled Compiling verilog file "Quinary_Adder.v" in library work Module compiled Compiling verilog file "Binary_Adder.v" in library work Module compiled Compiling verilog file "A_Reg_True_Complement.v" in library work Module compiled Compiling verilog file "Dwg_723832.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"Dwg_723832.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:852 - "Dwg_723832.v" line 37: Unconnected input port 'Reg_Q0_Calc' of instance 'T_B' is tied to GND. WARNING:Xst:852 - "Dwg_723832.v" line 37: Unconnected input port 'Reg_Q2_Calc' of instance 'T_B' is tied to GND. WARNING:Xst:852 - "Dwg_723832.v" line 37: Unconnected input port 'Reg_Q4_Calc' of instance 'T_B' is tied to GND. WARNING:Xst:852 - "Dwg_723832.v" line 37: Unconnected input port 'Reg_Q6_Calc' of instance 'T_B' is tied to GND. WARNING:Xst:852 - "Dwg_723832.v" line 37: Unconnected input port 'Reg_Q8_Calc' of instance 'T_B' is tied to GND. Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "Binary_Adder.v". Unit synthesized. Synthesizing Unit . Related source file is "Reg_Translator.v". Unit synthesized. Synthesizing Unit . Related source file is "Quinary_Adder.v". Unit synthesized. Synthesizing Unit . Related source file is "Mux2_TC.v". Unit synthesized. Synthesizing Unit . Related source file is "Reg_True_Complement.v". Unit synthesized. Synthesizing Unit . Related source file is "A_Reg_True_Complement.v". Unit synthesized. Synthesizing Unit . Related source file is "Dwg_723832.v". Unit synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : Dwg_723832.ngr Top Level Output File Name : Dwg_723832 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : Automotive 9500XL Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 45 Cell Usage : # BELS : 105 # AND2 : 62 # AND3 : 4 # AND4 : 2 # INV : 4 # OR2 : 27 # OR3 : 3 # OR4 : 2 # OR5 : 1 # IO Buffers : 45 # IBUF : 27 # OBUF : 18 ========================================================================= Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 2.16 secs --> Total memory usage is 127436 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered)