Dwg_723832 Project Status (01/14/2010 - 17:51:51)
Project File: Dwg_723832.ise Implementation State: Synthesized
Module Name: Dwg_723832
  • Errors:
 No Errors
Target Device: xa95*xl-**
  • Warnings:
 5 Warnings
Product Version:ISE 11.1
  • Routing Results:
  
Design Goal: Balanced
  • Timing Constraints:
  
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Jan 14 17:51:51 201005 Warnings0
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 01/14/2010 - 18:02:27