module Reg_True_Complement ( input True, Comp, Reg_1, Reg_Not_1, Reg_Q0, Reg_Q2, Reg_Q4, Reg_Q6, Reg_Q8, output Reg_B0_TC, Reg_B1_TC, Reg_Q0_TC, Reg_Q2_TC, Reg_Q4_TC, Reg_Q6_TC, Reg_Q8_TC ); // Fig 37, Drawing 723832 Mux2_TC B0 ( Reg_Not_1, Reg_1, True, Comp, Reg_B0_TC ); Mux2_TC B1 ( Reg_1, Reg_Not_1, True, Comp, Reg_B1_TC ); Mux2_TC Q0 ( Reg_Q0, Reg_Q8, True, Comp, Reg_Q0_TC ); Mux2_TC Q2 ( Reg_Q2, Reg_Q6, True, Comp, Reg_Q2_TC ); assign Reg_Q4_TC = Reg_Q4; Mux2_TC Q6 ( Reg_Q6, Reg_Q2, True, Comp, Reg_Q6_TC ); Mux2_TC Q8 ( Reg_Q8, Reg_Q0, True, Comp, Reg_Q8_TC ); endmodule