Dwg_723832 Project Status
Project File: Dwg_723832.ise Implementation State: New
Module Name: Reg_True_Complement
  • Errors:
 
Target Device: xa95*xl-**
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 12/17/2009 - 11:58:28