 
cpldfit:  version L.33                              Xilinx Inc.
                                  Fitter Report
Design Name: Dwg_729087                          Date:  1-15-2010,  4:31PM
Device Used: XA9536XL-15-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
10 /36  ( 28%) 16  /180  (  9%) 8  /108 (  7%)   5  /36  ( 14%) 12 /34  ( 35%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           6/18        2/54        8/90       6/17
FB2           4/18        6/54        8/90       6/17
             -----       -----       -----      -----    
             10/36        8/108      16/180     12/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :    12      28
Output        :   10          10    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     12          12

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 10 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - The signal(s) 'F4E' are in combinational feedback loops.
   These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the
   hazard reduction circuitry.
   Timing analysis of paths involving this node may be inaccurate or incomplete.
WARNING:Cpld - The signal(s) 'E2D' are in combinational feedback loops.
   These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the
   hazard reduction circuitry.
   Timing analysis of paths involving this node may be inaccurate or incomplete.
WARNING:Cpld:829 - Signal 'Clock_Ctl_OBUF.CLKF' has been minimized to 'GND'.
WARNING:Cpld:1007 - Removing unused input(s) 'Stop_Clock'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Start_Reset'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Process_Check_Reset'.  The
   input(s) are unused after optimization. Please verify functionality via
   simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Not_Print_SC_Comp_NPF'.  The
   input(s) are unused after optimization. Please verify functionality via
   simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Not_Print_Ready'.  The input(s)
   are unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Clock_Ctrl'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
*************************  Summary of Mapped Logic  ************************

** 10 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
Time_075_015_TR2    2     2     FB1_2   41   I/O     O       LOW  FAST RESET
Osc_2               1     1     FB1_4   42   I/O     O       LOW  FAST 
Not_Osc             1     1     FB1_8   3    I/O     O       LOW  FAST 
Osc_3               1     1     FB1_11  7    I/O     O       LOW  FAST 
STAR_Reset          1     1     FB1_15  14   I/O     O       LOW  FAST 
Time_015_075_TR2    2     2     FB1_17  18   I/O     O       LOW  FAST SET
Time_000_060_TR1    3     4     FB2_2   38   I/O     O       LOW  FAST SET
Time_060_000_TR1    3     4     FB2_8   31   I/O     O       LOW  FAST RESET
Osc_1               2     4     FB2_12  27   I/O     O       LOW  FAST 
Clock_Ctl           0     0     FB2_16  20   I/O     O       LOW  FAST SET

** 2 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
Time_045_105_TR4    FB2_9   30   I/O     I
Time_105_045_TR4    FB2_10  29   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               2/52
Number of signals used by logic mapping into function block:  2
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   40    I/O     
Time_075_015_TR2      2       0     0   3     FB1_2   41    I/O     O
(unused)              0       0     0   5     FB1_3   43    GCK/I/O 
Osc_2                 1       0     0   4     FB1_4   42    I/O     O
(unused)              0       0     0   5     FB1_5   44    GCK/I/O 
(unused)              0       0     0   5     FB1_6   2     I/O     
(unused)              0       0     0   5     FB1_7   1     GCK/I/O 
Not_Osc               1       0     0   4     FB1_8   3     I/O     O
(unused)              0       0     0   5     FB1_9   5     I/O     
(unused)              0       0     0   5     FB1_10  6     I/O     
Osc_3                 1       0     0   4     FB1_11  7     I/O     O
(unused)              0       0     0   5     FB1_12  8     I/O     
(unused)              0       0     0   5     FB1_13  12    I/O     
(unused)              0       0     0   5     FB1_14  13    I/O     
STAR_Reset            1       0     0   4     FB1_15  14    I/O     O
(unused)              0       0     0   5     FB1_16  16    I/O     
Time_015_075_TR2      2       0     0   3     FB1_17  18    I/O     O
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: Osc_2              2: Time_060_000_TR1 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
Time_075_015_TR2     XX...................................... 2
Osc_2                X....................................... 1
Not_Osc              X....................................... 1
Osc_3                X....................................... 1
STAR_Reset           X....................................... 1
Time_015_075_TR2     XX...................................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               6/48
Number of signals used by logic mapping into function block:  6
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   39    I/O     
Time_000_060_TR1      3       0     0   2     FB2_2   38    I/O     O
(unused)              0       0     0   5     FB2_3   36    GTS/I/O 
(unused)              0       0     0   5     FB2_4   37    I/O     
(unused)              0       0     0   5     FB2_5   34    GTS/I/O 
(unused)              0       0     0   5     FB2_6   33    GSR/I/O 
(unused)              0       0     0   5     FB2_7   32    I/O     
Time_060_000_TR1      3       0     0   2     FB2_8   31    I/O     O
(unused)              0       0     0   5     FB2_9   30    I/O     I
(unused)              0       0     0   5     FB2_10  29    I/O     I
(unused)              0       0     0   5     FB2_11  28    I/O     
Osc_1                 2       0     0   3     FB2_12  27    I/O     O
(unused)              0       0     0   5     FB2_13  23    I/O     
(unused)              0       0     0   5     FB2_14  22    I/O     
(unused)              0       0     0   5     FB2_15  21    I/O     
Clock_Ctl             0       0     0   5     FB2_16  20    I/O     O
(unused)              0       0     0   5     FB2_17  19    I/O     
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: Clock_Ctl          3: Osc_2              5: Time_060_000_TR1 
  2: Osc_1              4: Time_045_105_TR4   6: Time_105_045_TR4 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
Time_000_060_TR1     .X.XXX.................................. 4
Time_060_000_TR1     .X.XXX.................................. 4
Osc_1                X.XXX................................... 4
Clock_Ctl            ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_Clock_Ctl: FTCPE port map (Clock_Ctl,'0','0','0','0');


Not_Osc <= NOT Osc_2;


Osc_1 <= ((NOT Osc_2)
	OR (NOT Time_060_000_TR1 AND Time_045_105_TR4 AND NOT Clock_Ctl));


Osc_2 <= NOT Osc_2;


Osc_3 <= NOT Osc_2;


STAR_Reset <= NOT Osc_2;

FDCPE_Time_000_060_TR1: FDCPE port map (Time_000_060_TR1,Time_000_060_TR1_D,NOT Osc_1,'0','0');
Time_000_060_TR1_D <= ((NOT Time_060_000_TR1 AND Time_105_045_TR4)
	OR (Time_105_045_TR4 AND NOT Time_045_105_TR4));

FDCPE_Time_015_075_TR2: FDCPE port map (Time_015_075_TR2,NOT Time_060_000_TR1,NOT Osc_2,'0','0');

FDCPE_Time_060_000_TR1: FDCPE port map (Time_060_000_TR1,Time_060_000_TR1_D,NOT Osc_1,'0','0');
Time_060_000_TR1_D <= ((NOT Time_060_000_TR1 AND Time_105_045_TR4)
	OR (Time_105_045_TR4 AND NOT Time_045_105_TR4));

FDCPE_Time_075_015_TR2: FDCPE port map (Time_075_015_TR2,Time_060_000_TR1,NOT Osc_2,'0','0');

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XA9536XL-15-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5        XA9536XL-15-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 KPR                           
  2 KPR                              24 TDO                           
  3 Not_Osc                          25 GND                           
  4 GND                              26 VCC                           
  5 KPR                              27 Osc_1                         
  6 KPR                              28 KPR                           
  7 Osc_3                            29 Time_105_045_TR4              
  8 KPR                              30 Time_045_105_TR4              
  9 TDI                              31 Time_060_000_TR1              
 10 TMS                              32 KPR                           
 11 TCK                              33 KPR                           
 12 KPR                              34 KPR                           
 13 KPR                              35 VCC                           
 14 STAR_Reset                       36 KPR                           
 15 VCC                              37 KPR                           
 16 KPR                              38 Time_000_060_TR1              
 17 GND                              39 KPR                           
 18 Time_015_075_TR2                 40 KPR                           
 19 KPR                              41 Time_075_015_TR2              
 20 Clock_Ctl                        42 Osc_2                         
 21 KPR                              43 KPR                           
 22 KPR                              44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xa95*xl-*-*
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : LOW
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
