Release 11.1 - xst L.33 (lin) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.06 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.06 secs --> Reading design: Dwg_729087.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Dwg_729087.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "Dwg_729087" Output Format : NGC Target Device : Automotive 9500XL ---- Source Options Top Module Name : Dwg_729087 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Library Search Order : Dwg_729087.lso Keep Hierarchy : YES Netlist Hierarchy : as_optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/RK__.v" in library work Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" in library work Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" in library work Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/AED_.v" in library work Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" in library work Module compiled Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/PQ___B.v" in library verilog Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/PQ___A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/PP___B.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/PP___A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JLVB_P.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_P.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_G.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_C.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JGVW_A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/JFVN_A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGQ__H.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__F.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__D.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/DAB__G.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CQZV_A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CNWT_H.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CNWT_B.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__G.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__F.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__A.v" in library verilog Module compiled Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/AM___B.v" in library verilog Module compiled Module compiled No errors in compilation Analysis of file <"Dwg_729087.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 32: Unconnected input port 'F' of instance 'A4' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 42: Unconnected input port 'E' of instance 'B5' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 42: Unconnected input port 'P' of instance 'B5' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 42: Unconnected input port 'B' of instance 'B5' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 42: Unconnected input port 'C' of instance 'B5' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 50: Unconnected input port 'E' of instance 'C6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 50: Unconnected input port 'P' of instance 'C6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 50: Unconnected input port 'B' of instance 'C6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 50: Unconnected input port 'C' of instance 'C6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'B' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'C' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'D' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'E' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'F' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'G' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 53: Unconnected input port 'H' of instance 'D2' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'A' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'C' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'D' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'E' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'F' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'G' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 65: Unconnected input port 'H' of instance 'E3' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 75: Unconnected input port 'E' of instance 'F6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 75: Unconnected input port 'P' of instance 'F6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 75: Unconnected input port 'B' of instance 'F6' is tied to GND. WARNING:Xst:852 - "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v" line 75: Unconnected input port 'C' of instance 'F6' is tied to GND. Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" line 12: Delay is ignored for synthesis. WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" line 13: Delay is ignored for synthesis. WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" line 14: Delay is ignored for synthesis. WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" line 15: Delay is ignored for synthesis. WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v" line 16: Delay is ignored for synthesis. Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming a as a_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming b as b_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming c as c_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming e as e_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming f as f_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming g as g_rnm0). WARNING:Xst:863 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v" line 1: Name conflict ( and , renaming h as h_rnm0). Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/RK__.v" line 7: Delay is ignored for synthesis. WARNING:Xst:916 - "/../../../../../../../users/vsnyder/1401/verilog/SMS/RK__.v" line 9: Delay is ignored for synthesis. Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__F.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JLVB_P.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/PP___B.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__G.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__F.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JFVN_A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/AED_.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input

is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. INFO:Xst:1608 - Relative priorities of control signals on register differ from those commonly found in the selected device family. This will result in additional logic around the register. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CEA_.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CAC__A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JGVW_A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CM__.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_G.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/PQ___A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/DAB__G.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/PP___A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/AM___B.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CNWT_B.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_C.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/PQ___B.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CNWT_H.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/RK__.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_P.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__D.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGP__A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/CQZV_A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/JJVN_A.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/SMS/DGQ__H.v". Unit synthesized. Synthesizing Unit . Related source file is "/../../../../../../../users/vsnyder/1401/verilog/Dwg_729087/Dwg_729087.v". Unit synthesized. WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 3 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Registers : 3 Flip-Flops : 3 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2170 - Unit RK__ : the following signal(s) form a combinatorial loop: A. Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... WARNING:Xst:2170 - Unit A2 : the following signal(s) form a combinatorial loop: F, E, H3/A, Dwg_729087/N1, H2/G, Dwg_729087/F4E, F1, Dwg_729087/_or0000, H2/C, H3/A1, Dwg_729087/N7, H3/H, F4/H, Dwg_729087/H3H, Dwg_729087/A2E. ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : Dwg_729087.ngr Top Level Output File Name : Dwg_729087 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : Automotive 9500XL Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 18 Cell Usage : # BELS : 55 # AND2 : 1 # GND : 3 # INV : 37 # OR2 : 10 # OR3 : 1 # VCC : 3 # FlipFlops/Latches : 3 # FDCPE : 3 # IO Buffers : 18 # IBUF : 8 # OBUF : 10 ========================================================================= Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 2.23 secs --> Total memory usage is 128236 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 71 ( 0 filtered) Number of infos : 1 ( 0 filtered)