This report is the result of a static timing analysis of your design after it has been fit in the device that you selected. The timing values given represent the worst-case values over the recommended operating conditions for the part.
The timing report consists of a series of sections:
This table summarizes the external timing parameters for your device, including tPD, tCO, tSU, tCYC, and fSYSTEM. For a more detailed description of the timing model for your device, please refer to the application notes linked below.
This section reports on any timing constraints that you created for your design. Timing constraints can be entered using the Constraints Editor tool, or by editing an Implementation Constraints File directly. For more information on creating timing constraints, see the Constraints Guide.
Note that if you did not define any constraints for your design, then the timing analysis software will automatically create a default set of constraints for you. These include pad-to-pad, register-to-register, pad-to-register, and period constraints. A constraint value of 0 ns will be used for all of these automatically generated constraints. As a result, all paths listed under each constraint will violate the constraint, and will have a negative value for slack.
Note also that to limit the size of the report, each path endpoint involved in a timing path will only be listed once, under a single constraint.
For each timing path listed under a constraint, there is a hyperlink that can be used to open a window listing the individual internal delay elements traversed in the path. To understand these delay elements, consult the Definitions section below, or the following application notes and white papers:
XAPP375: Understanding the CoolRunner-II Timing Model
WP122: Using the CoolRunner XPLA3 Timing Model
XAPP071: Using the XC9500 Timing Model
XAPP111: Using the XC9500XL Timing Model
XAPP 362: Using the XC9500XV Timing Model
available in the literature section of www.xilinx.com.
This section of the report lists the external timing parameters for your design. This includes; maximum external clock speed for each clock, setup and hold times for each registered input, clock-to-output pad timing for each registered output, clock to setup time for each register-to-register timing path, and pad-to-pad time for each combinatorial path through your design.
To do more advanced timing analysis of your design, select the process Analyze Post-Fit Static Timing in iSE. This will run Xilinx's Timing Analyzer tool interactively. The Timing Analyzer provides a powerful, flexible, and easy way to perform static timing analysis on FPGA and CPLD designs. With Timing Analyzer, analysis can be performed immediately after mapping, placing or routing an FPGA design, and after fitting and routing a CPLD design.
Timing Analyzer verifies that the delay along a given path or paths meets specified timing requirements. It organizes and displays data that allows you to analyze critical paths in a circuit, the cycle time of the circuit, the delay along any specified path(s), and the path with the greatest delay. It also provides a quick analysis of the effect different speed grades have on the same design.
Timing Analyzer performs setup and hold checks (skew analysis). It works with synchronous systems composed of synchronous elements and combinatorial logic. In synchronous design, Timing Analyzer takes into account all path delays, including clock-to-out and setup requirements, while calculating the worst-case timing of the design.
Timing Analyzer creates timing analysis reports based on existing timing constraints or user specified paths within the program. Timing reports have a hierarchical browser to quickly jump to different sections of the reports. Timing paths in reports can be cross probed to synthesis tools (Exemplar and Synplicity) and Floorplanner.
There are several ways to issue commands in Timing Analyzer. Timing Analyzer can be controlled through GUI features (menu commands) or its comprehensive macro command language facility. You can select from menus, click toolbar buttons, type keyboard commands in the console window, and run macros.
Reports pad to pad paths that start at input pads and end at output pads. The maximum external pad to pad delay. Combinatorial pad-to-pad paths begin at input pads, propagate through one or more levels of combinatorial logic and end at output pads. Combinatorial paths also trace through the enable inputs of 3-state controlled pads. Combinatorial paths are not traced through clock, and asynchronous set and reset inputs of registers. These paths are also broken at bidirectional pins
The maximum external clock pad to output pad delay. Reports paths that start at input pads trace through clock inputs of registers and end at output pads. Paths are not traced through PRE/CLR inputs of registers. You can directly specify tCO for all registered output paths in your design using the Pad-to-Pad timespec. Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate through global clock buffers, and propagate through the flip-flop Q output and any number of levels of combinatorial logic and end at the output pad. Clock-Pad-to-Pad paths for product term clock paths begin at input pads, propagate through any number of logic levels feeding into a clock product term, propagate through the flip-flop Q output and any number of levels of combinatorial logic and end at the output pad. Clock-Pad-to-Pad paths also trace through the enable inputs of 3-state controlled pads.
Reports external setup time of data to clock at pad. Data path starts at an input pad and ends at register (Fast Input Register for tSUF) D/T input. Clock path starts at input pad and ends at the register clock input. Paths are not traced through registers. Pin-to-pin setup requirement is not reported or guaranteed for product-term clocks derived from macrocell feedback signals.
The minimum required setup time for flip-flops. You can specify the tSU (setup-to-clock) for all inputs in your design relative to a global clock or product term clock. Each tSU OFFSET timespec involves an input path and a clock path. Input paths start at input pads, propagate through input buffers and any number of combinatorial logic levels before ending at a flip-flop D/T input, including the receiving flip-flop's tSU. Input paths are not traced through flip-flop clock pins, asynchronous set/reset inputs or bidirectional I/O pins. Global clock paths start at global clock pads, propagate through global clock buffers and end at the flip-flop clock pin. Product term clock paths start at input pads, propagate through a single level of logic implemented in a clock product term and end at the flip-flop clock pin.
Register to register cycle time. Includes source register tCO and destination register tSU.
Note that when the computed Maximum Clock Speed is limited by tCYC, it is computed assuming that all registers are rising-edge sensitive.
Maximum clock operating frequency. You can specify the fSYSTEM (clock frequency or period) for all registered paths in your design using a Register-to-Register timespec. Register-to-Register paths begin at flip-flop clock inputs, propagate through the flip-flop Q output and any number of levels of combinatorial logic and end at the receiving flip-flop D/T input, including the receiving flip-flop's tSU. When these flip-flops are clocked by the same clock, the delay on this path is equivalent to the cycle time of the clock. Registered paths do not propagate through clock, and asynchronous set and reset inputs of registers as shown below. These paths are also broken at bidirectional pins.