Release 11.1 - xst L.33 (lin) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to /home/vsnyder/1401/verilog/Dwg_729087/xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.16 secs --> Parameter xsthdpdir set to /home/vsnyder/1401/verilog/Dwg_729087/xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.17 secs --> ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "../SMS/JGVW.v" in library work Module compiled No errors in compilation Analysis of file <"JGVW.prj"> succeeded. Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.18 secs --> Total memory usage is 126584 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)