Release 11.1 - xst L.33 (lin) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to /users/vsnyder/1401/verilog/Dwg_729087/xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> Parameter xsthdpdir set to /users/vsnyder/1401/verilog/Dwg_729087/xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "/../../../../../../../users/vsnyder/1401/verilog/SMS/PQ___B.v" in library verilog Module compiled No errors in compilation Analysis of file <"PQ___B.prj"> succeeded. Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.06 secs --> Total memory usage is 118676 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)