module qui_bi ( A_Reg_Q0, A_Reg_Q2, A_Reg_Q4, A_Reg_Q6, A_Reg_Q8, B_Reg_Q0, B_Reg_Q2, B_Reg_Q4, B_Reg_Q6, B_Reg_Q8, Q0_Not_Carry, Q0_Carry, Q2_Not_Carry, Q2_Carry, Q4_Not_Carry, Q4_Carry, Q6_Not_Carry, Q6_Carry, Q8_Not_Carry ); input A_Reg_Q0, A_Reg_Q2, A_Reg_Q4, A_Reg_Q6, A_Reg_Q8, B_Reg_Q0, B_Reg_Q2, B_Reg_Q4, B_Reg_Q6, B_Reg_Q8; output Q0_Not_Carry, Q0_Carry, Q2_Not_Carry, Q2_Carry, Q4_Not_Carry, Q4_Carry, Q6_Not_Carry, Q6_Carry, Q8_Not_Carry; wor G_Q0_Carry, G_Q2_Not_Carry, G_Q2_Carry, G_Q4_Not_Carry, G_Q4_Carry, G_Q6_Not_Carry, G_Q6_Carry, G_Q8_Not_Carry; assign Q0_Not_Carry = A_Reg_Q0 & B_Reg_Q0; assign G_Q0_Carry = A_Reg_Q2 & B_Reg_Q8; assign G_Q0_Carry = A_Reg_Q4 & B_Reg_Q6; assign G_Q0_Carry = A_Reg_Q6 & B_Reg_Q4; assign G_Q0_Carry = A_Reg_Q8 & B_Reg_Q2; assign Q0_Carry = G_Q0_Carry; assign G_Q2_Not_Carry = A_Reg_Q0 & B_Reg_Q2; assign G_Q2_Not_Carry = A_Reg_Q2 & B_Reg_Q0; assign Q2_Not_Carry = G_Q2_Not_Carry; assign G_Q2_Carry = A_Reg_Q4 & B_Reg_Q8; assign G_Q2_Carry = A_Reg_Q6 & B_Reg_Q6; assign G_Q2_Carry = A_Reg_Q6 & B_Reg_Q4; assign Q2_Carry = G_Q2_Carry; assign G_Q4_Not_Carry = A_Reg_Q0 & B_Reg_Q4; assign G_Q4_Not_Carry = A_Reg_Q2 & B_Reg_Q2; assign G_Q4_Not_Carry = A_Reg_Q4 & B_Reg_Q0; assign Q4_Not_Carry = G_Q4_Not_Carry; assign G_Q4_Carry = A_Reg_Q6 & B_Reg_Q8; assign G_Q4_Carry = A_Reg_Q8 & B_Reg_Q6; assign Q4_Carry = G_Q4_Carry; assign G_Q6_Not_Carry = A_Reg_Q0 & B_Reg_Q6; assign G_Q6_Not_Carry = A_Reg_Q2 & B_Reg_Q4; assign G_Q6_Not_Carry = A_Reg_Q4 & B_Reg_Q2; assign G_Q6_Not_Carry = A_Reg_Q6 & B_Reg_Q0; assign Q6_Not_Carry = G_Q6_Not_Carry; assign Q6_Carry = A_Reg_Q8 & B_Reg_Q0; assign G_Q8_Not_Carry = A_Reg_Q0 & B_Reg_Q8; assign G_Q8_Not_Carry = A_Reg_Q2 & B_Reg_Q6; assign G_Q8_Not_Carry = A_Reg_Q4 & B_Reg_Q4; assign G_Q8_Not_Carry = A_Reg_Q8 & B_Reg_Q2; assign G_Q8_Not_Carry = A_Reg_Q8 & B_Reg_Q0; assign Q8_Not_Carry = G_Q8_Not_Carry; endmodule