Timing Report

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Design Name	Dwg_729087
Device, Speed (SpeedFile Version)	XA9536XL, -15 (3.1)
Date Created	Fri Jan 15 16:25:26 2010
Created By	Timing Report Generator: version L.33
Copyright	Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Combinatorial feedback is detected on the clock path at signal 'Osc_2'. Timing analysis of paths involving this node may be inaccurate or incomplete.
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'Time_060_000_TR1.CLKF' has multiple original clock nets 'Clock_Ctl_OBUF.Q' 'Time_060_000_TR1_OBUF.Q' 'Time_045_105_TR4'.
Possible asynchronous logic: Clock pin 'Time_000_060_TR1.CLKF' has multiple original clock nets 'Clock_Ctl_OBUF.Q' 'Time_060_000_TR1_OBUF.Q' 'Time_045_105_TR4'.

Performance Summary
Min. Clock Period	15.500 ns.
Max. Clock Frequency (fSYSTEM)	64.516 MHz.
Limited by Cycle Time for Clock_Ctl_OBUF.Q
Clock to Setup (tCYC)	15.500 ns.
Pad to Pad Delay (tPD)	15.500 ns.
Setup to Clock at the Pad (tSU)	-5.600 ns.
Clock Pad to Output Pad Delay (tCO)	46.200 ns.

Timing Constraints

Constraint Name	Requirement (ns)	Delay (ns)	Paths	Paths Failing
TS1000	0.0	0.0	0	0
TS1001	0.0	0.0	0	0
TS1002	0.0	0.0	0	0
TS1003	0.0	0.0	0	0
TS1004	0.0	0.0	0	0
TS1005	0.0	0.0	0	0
AUTO_TS_F2F	0.0	15.5	4	4
AUTO_TS_P2P	0.0	46.2	4	4
AUTO_TS_P2F	0.0	19.4	6	6
AUTO_TS_F2P	0.0	17.2	3	3

Constraint: TS1000

**Description: PERIOD:PERIOD_Time_015_075_TR2_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1001

**Description: PERIOD:PERIOD_Clock_Ctl_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1002

**Description: PERIOD:PERIOD_Time_075_015_TR2_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1003

**Description: PERIOD:PERIOD_Clock_Ctl_OBUF.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1004

**Description: PERIOD:PERIOD_Time_060_000_TR1_OBUF.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1005

**Description: PERIOD:PERIOD_Time_045_105_TR4:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_F2F

**Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
Time_060_000_TR1.Q to Time_000_060_TR1.D	0.000	15.500	-15.500
Time_060_000_TR1.Q to Time_015_075_TR2.D	0.000	15.500	-15.500
Time_060_000_TR1.Q to Time_060_000_TR1.D	0.000	15.500	-15.500
Time_060_000_TR1.Q to Time_075_015_TR2.D	0.000	15.500	-15.500

Constraint: AUTO_TS_P2P

**Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
Time_045_105_TR4 to Time_000_060_TR1	0.000	46.200	-46.200
Time_045_105_TR4 to Osc_1	0.000	38.300	-38.300
Time_045_105_TR4 to Time_060_000_TR1	0.000	25.100	-25.100
Time_045_105_TR4 to Osc_1	0.000	15.500	-15.500

Constraint: AUTO_TS_P2F

**Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
Time_045_105_TR4 to Time_000_060_TR1.CLKF	0.000	19.400	-19.400
Time_045_105_TR4 to Time_060_000_TR1.CLKF	0.000	19.400	-19.400
Time_045_105_TR4 to Time_000_060_TR1.D	0.000	13.800	-13.800

Constraint: AUTO_TS_F2P

**Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
Time_060_000_TR1.Q to Osc_1	0.000	17.200	-17.200
Time_000_060_TR1.Q to Time_000_060_TR1	0.000	4.000	-4.000
Time_060_000_TR1.Q to Time_060_000_TR1	0.000	4.000	-4.000

Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock	fEXT (MHz)	Reason
Clock_Ctl_OBUF.Q	64.516	Limited by Cycle Time for Clock_Ctl_OBUF.Q
Time_060_000_TR1_OBUF.Q	64.516	Limited by Cycle Time for Time_060_000_TR1_OBUF.Q
Time_045_105_TR4	64.516	Limited by Cycle Time for Time_045_105_TR4

Setup/Hold Times for Clocks

**Setup/Hold Times for Clock Clock_Ctl.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
Time_045_105_TR4	-7.300	10.800
Time_105_045_TR4	-7.300	10.800

**Setup/Hold Times for Clock Time_060_000_TR1.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
Time_045_105_TR4	-7.300	10.800
Time_105_045_TR4	-7.300	10.800

**Setup/Hold Times for Clock Time_045_105_TR4**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
Time_105_045_TR4	-5.600	9.100

Clock to Pad Timing

**Clock Time_045_105_TR4 to Pad**
Destination Pad	Clock (edge) to Pad
Time_000_060_TR1	46.200
Osc_1	38.300
Time_060_000_TR1	25.100

Clock to Setup Times for Clocks

**Clock to Setup for clock Clock_Ctl.Q**
Source	Destination	Delay
Time_060_000_TR1.Q	Time_000_060_TR1.D	15.500
Time_060_000_TR1.Q	Time_060_000_TR1.D	15.500

**Clock to Setup for clock Time_060_000_TR1.Q**
Source	Destination	Delay
Time_060_000_TR1.Q	Time_000_060_TR1.D	15.500
Time_060_000_TR1.Q	Time_060_000_TR1.D	15.500

**Clock to Setup for clock Time_045_105_TR4**
Source	Destination	Delay
Time_060_000_TR1.Q	Time_000_060_TR1.D	15.500
Time_060_000_TR1.Q	Time_060_000_TR1.D	15.500

Pad to Pad List

Source Pad	Destination Pad	Delay
Time_045_105_TR4	Osc_1	15.500

Number of paths analyzed: 17
Number of Timing errors: 17
Analysis Completed: Fri Jan 15 16:25:26 2010